October 5, 2004 10:45am -11:45am at David's Restaurant Santa Clara, CA
Morgan Hill, California - October 1, 2004. OEA International, Inc. (OEA), the industry leader in 3D interconnect extraction, invites you to attend technical presentation on 65nm and 90nm interconnect modeling challenges which will take place at FSA Design Modeling Workshop on October 5, 2004 at 10:45 am at David's Restaurant, Santa Clara, CA.
As the minimum metal dimensions shrink below 0.18 microns, it has become standard practice to employ uniform metal density rules on all layers of metal to achieve an acceptable yield on IC processes. This is typically accomplished by two methods, slotting and dummy metal fill. These two methods are jointly used depending on the metal densities on the metal layout determined by the design. So, each layer of metal layout is checked according to its fill ratio in a set window size for each metal layer. The fill ratio and the area size of the check performed are layer, foundry and process dependent. If the fill ratio is larger than a given value there is a need for slotting the continuous large metal areas. If it is less than a different value, than the dummy metal fill rule is applied. Detailed rules for creating the slotting and dummy metal fill are layer, foundry and process dependent. Thus, the resulting metal geometry on silicon is no longer controlled only by the designer's layout, but is also affected by the resulting post-processing to control metal densities. If this post-processing is performed by the foundry rather than the designer, the metal layout can be largely different than the designer simulated and thought was correct. Since for the majority of high-speed designs, interconnect parasitics determine the IC performance, this creates a very difficult dilemma for the designer. This means, the effects of slotting and dummy metal fill have to be calculated during the design and extraction process.
In this paper, we present the effects of typical slotting and dummy metal fill methods on the interconnect performance from a three-dimensional mathematical modeling standpoint. The dummy metal fill, which creates floating metals, is investigated as to how it impacts the boundary conditions necessary for the solution of the Laplace equation. It is shown that this boundary condition due to the dummy metal fill impacts the capacitance greatly and thus changes the performance. In a similar way, slotting changes the resistance and the inductance of the metal interconnects. The methodology of taking those into consideration, again from the extraction point of view, is investigated. Since on-chip Spiral inductors are being widely used and their layout requires slotting and dummy metal fill together, due to the nature of their design, their impact is greatly pronounced. As a result, all of these combined effects are shown in three-dimensional Spiral inductance modeling for a variety of test cases. Because of the complications of a Spiral design, it makes it an interesting case from the application and creates a challenging modeling problem.
PRESENTATION LOCATION AND TIME
OEA International presentation will start at 10:45 am on October 5 and will take place at:
FSA Design Modeling Workshop
5151 Stars and Stripes Drive
Santa Clara, CA 95054
TO GET MORE IFORMATION ABOUT THIS PRESENTATION
Please call Alla Toy at (408) 778-6747 or email Email Contact
FSA DESIGN MODELING WORKSHOP INFORMATION
For more information on FSA Design Modeling Workshop and register to attend please visit http://www.fsa.org/suppliers_expo/tech_conference/modeling.asp
About OEA International
OEA International, Inc. is the industry leader in 3D extraction of interconnects. OEA's tools are currently used in the most demanding extraction and design environments. Some of the world's most advanced design facilities use OEA tools for detailed analysis and design of high-speed clocks, buses, I/O rings, and power grids. For additional information call (408) 778-6747, or visit OEA online at www.oea.com
Marketing Specialist, OEA International