PLDA GROUP Announces Tighter Collaboration with Xilinx on Vivado HLS to Enhance Software Programmability of Xilinx FPGAs in QuickPlay
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PLDA GROUP Announces Tighter Collaboration with Xilinx on Vivado HLS to Enhance Software Programmability of Xilinx FPGAs in QuickPlay

Users of QuickPlay 2.1 can now benefit from a streamlined flow to integrate Vivado HLS kernels within QuickPlay and benefit from the most advanced High Level Synthesis tool for FPGA

SAN JOSE, Calif. — (BUSINESS WIRE) — August 2, 2016 — In 2015 PLDA GROUP launched QuickPlay®, a software-defined FPGA development environment that aims at expanding the use of FPGA in data center, video/broadcast, and vision applications, by enabling non FPGA experts to develop FPGA accelerated systems easily and efficiently. By leveraging the right programming model, natively supporting the right programming language, fully abstracting the underlying FPGA hardware and providing access to powerful and affordable IP (through its recent launch of QuickStore), QuickPlay is able to significantly reduce the barriers to FPGA adoption.

With the latest release of QuickPlay, version 2.1, users can now benefit from an integrated flow to use Vivado® HLS kernels within their QuickPlay designs, benefitting from a state of the art HLS engine for FPGA while keeping the benefit of QuickPlay’s truly Software Defined development flow.

Launched in 2011, Vivado HLS is a widely used High Level Synthesis engine among Xilinx® designers with a fast ramping adoption rate. Vivado HLS brings productivity gains by delivering efficient hardware code from functions written in C++ and therefore provides a powerful and efficient High Level Synthesis engine for processing kernels used in QuickPlay.
“QuickPlay users are very positive about the overall QuickPlay experience and praise the tool for its ease of use and overall efficiency,” said Stephane Monboisset, Marketing Director for QuickPlay. “However, some of the most advanced users are looking at pushing the performance levels of their C kernels without having to go all the way to writing HDL code. We are pleased to allow them to do so by taking full advantage of the Quality of Result of Vivado HLS within their QuickPlay designs”.

While QuickPlay users benefit from the ease of integration of pre-built IP cores to create their custom accelerators on FPGA cards, most customize their accelerators with their own C processing functions. While QuickPlay’s built-in HLS engine is user friendly and produces good performance results, customers wanting to push the limits on specific processing kernels now have the option to use Vivado HLS seamlessly, and benefit from its unparalleled efficiency in terms of performance and logic footprint.

“Vivado HLS has been rapidly adopted by our customers, as C/C++ provides an order of magnitude in productivity gains for design and verification over hardware description languages” said Ramine Roane, Sr Director of Tools Marketing at Xilinx “QuickPlay brings a new and promising Software Defined flow to FPGA development and Vivado HLS integration in QuickPlay enhances software programmability for our devices for a wide range of application, such as Data Center workload acceleration, broadcast and vision.”

Product Availability:
QuickPlay v2.1 is available today and supports numerous boards from Xilinx, ReFLEX and Image Matters. More FPGA platforms are being added. The tool can be evaluated at no cost. Please visit QuickPlay online at or contact the QuickPlay team for details.

About QuickPlay
QuickPlay is a PLDA GROUP ( brand that aims to accelerate the adoption of FPGA-based reconfigurable hardware in IT infrastructures by opening up FPGA design to non-hardware experts. The QuickPlay software IDE enables developers with different engineering backgrounds to model, design, debug, and deploy FPGA hardware as their end product or as a part of their final system, all without FPGA expertise, and without the pain and time traditionally associated with FPGA design. QuickPlay features a pure graphical and C/C++ design methodology that abstracts the hardware design and debug process, streamlines the mapping of the FPGA design on the hardware target, and completely hides the details of hardware implementation, for a user experience that compares with traditional software programming. QuickPlay is the result of years of research in the field of High-Level Design (HLD) and High-Level Synthesis (HLS) combined with PLDA GROUP strong expertise in FPGA hardware and IP design. QuickPlay enables leading technology companies to rip the benefits of FPGA without the pain, in domains such as Cloud computing, Vision, A/V broadcast, data center networking, HPC and more.


Stéphane Hauradou
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