Aldec delivers enhanced UVM Support and New Debugging Features with the latest release of Riviera-PRO
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Aldec delivers enhanced UVM Support and New Debugging Features with the latest release of Riviera-PRO

Henderson, NV – March 09, 2016 –  Aldec, Inc., today announces the latest release of  Riviera-PRO™ 2016.02 - Advanced Verification Platform. Riviera-PRO is a tightly integrated solution for functional verification of complex System on Chip (SoC), ASIC and FPGA designs. This new release of Riviera-PRO brings enhanced support for Universal Verification Methodology (UVM) and significant performance improvements in simulation and verification along with new debugging features added to increase the verification productivity.

The complexities of today’s designs are driving the adoption of Universal Verification Methodology (UVM) higher and higher. While Universal Verification Methodology (UVM) does bring a cutting edge verification solution to simulation doorstep but along comes the performance bottleneck.

“Verification of complex designs using a simulation-based approach poses the big challenge of writing enough test vectors,” said Satyam Jani, Riviera-PRO Product Manager “SystemVerilog constraint randomization offers a nice solution to this issue, but at this point the performance of simulator becomes more critical. Aldec has always worked diligently to improve the simulation performance for such advanced verification techniques and, with this release of Riviera-PRO 2016.02, we have significantly improved the performance for random constraints with expressions containing the division operator (/) or linear equations.”

In addition to rolling out official support for Windows® 10, Riviera-PRO 2016.02 also introduces a new debugging tool, Design Units Window. This feature allows users to easily list the design units from multiple simulation dataset. Design Unit Window also shows coverage data on a per-unit basis from the coverage results of live simulation.

The 2016.02 release of Riviera-PRO also includes numerous new features, enhancements, and performance optimizations.For additional information, tutorials, free evaluation download and What’s New Presentation, visit

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions.