Cadence Announces New OrCAD Technology to Help Shorten PCB Design Cycles; PSpice Enhancements Provide Highest Level of Integration Between Analog Simulator and MathWorks' MATLAB

SAN JOSE, Calif.—(BUSINESS WIRE)—Aug. 11, 2004— Cadence Design Systems, Inc. (NYSE: CDN) (Nasdaq: CDN) today announced new PSpice-based simulation technology for the OrCAD(R) product line, enabling shortened PCB design cycles for the power electronics, military/aerospace, and automotive industries. Seamlessly integrating proven Cadence(R) PSpice(R) technology with industry-leading MATLAB(R) and Simulink(R) products from The MathWorks, the new PSpice SLPS interface, co-developed by Cadence and Cybernet Systems in Japan, allows co-simulation of electrical and mechanical systems, making it easier to detect critical issues early in the design cycle. When combined with the stress analysis capabilities of the new PSpice Smoke option, the reliability of designs can be analyzed and improved earlier in the design cycle.

"We welcome this integration between PSpice and our MATLAB and Simulink products," said Jim Tung, MathWorks Fellow at The MathWorks. "This is a significant step in the right direction to leverage advanced, cost-effective PCB design solutions with our Model-Based Design tools in the automotive, military/aerospace, and power electronics industries."

Currently, many companies design and test the electronics separately from the system level. With this approach, integration issues often aren't discovered until the prototype phase, causing critical time delays in getting a product to market. The new integration offered with the PSpice SLPS interface and the MATLAB and Simulink products helps designers avoid this problem. In many cases, this can achieve a successful system design with only one prototype.

The PSpice SLPS simulation environment supports the substitution of an actual electronic block, allowing co-simulation with MATLAB and Simulink and thereby enabling the designer to identify and correct integration issues of electronics within a system. This helps identify errors earlier in the design process, which can save time and money often spent in debugging trial boards within system designs. With the PSpice Smoke option, designers can perform a stress audit to verify that electrical components are operating within the manufacturers' safe operating limits or de-rated limits. The Smoke tool flags violations such as power dissipation, secondary breakdown limits, current/voltage and junction temperature limits. Because thermal violations are detected at the design level, design re-spins can be minimized.

"The latest additions to the OrCAD product line further demonstrate our ongoing commitment to this market and, most importantly, the PCB designers we serve," said Steve Kamin, director of the OrCAD product line at Cadence. "Cadence is a pioneer in the field of PCB design and this new technology demonstrates our continuing efforts to develop innovative OrCAD solutions."

The PSpice SLPS interface and the PSpice Smoke option, available now, fit seamlessly into a front-to-back PCB design flow for power electronics; the PSpice product is already part of OrCAD Capture to OrCAD Layout and OrCAD Capture to Allegro PCB flows.

OrCAD products are distributed by a worldwide network of solution providers. For more information on OrCAD, please visit www.orcad.com.

About Cadence

Cadence is the world's largest supplier of electronic design technologies and engineering services. Cadence products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics based products. With approximately 4,850 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and trades on both the New York Stock Exchange and Nasdaq under the symbol CDN. More information is available at www.cadence.com.

Cadence, the Cadence logo, OrCAD, PSpice and Allegro are registered trademarks of Cadence Design Systems. MATLAB and Simulink are registered trademarks of The MathWorks, Inc. All other trademarks are the property of their respective owners.



Contact:
The Hoffman Agency for Cadence Design Systems
Molly Taylor, 408-975-3067

Email Contact



Review Article Be the first to review this article
CST: Webinar

Aldec Simulator Evaluate Now

Featured Video
Jobs
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Senior Formal FAE Location OPEN for EDA Careers at San Jose or Anywhere, CA
Design Verification Engineer for Cirrus Logic, Inc. at Austin, TX
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
RF IC Design Engineering Manager for Intel at Santa Clara, CA
Upcoming Events
IC Open Innovation Panel During REUSE 2017 at Santa Clara Convention Center 5001 Great America Parkway Santa Clara CA - Dec 14, 2017
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise