Allegro Platform Version 15.2 Improves Constraint-Driven PCB Design FlowSAN JOSE, Calif.—(BUSINESS WIRE)—July 19, 2004— Cadence Design Systems, Inc. (NYSE: CDN) today introduced a new release of its Cadence(R) Allegro(R) system interconnect design platform with features designed to shorten the PCB design cycle and provide significant productivity gains. Allegro platform version 15.2 takes constraint-driven PCB design to the next level and brings multiple new products to market that address the ever-evolving design challenges of integrated chip (IC) packaging and multi-gigahertz (MGH) signals. The Allegro platform, version 15.2, introduces innovative collaborative design and library data management solutions.
"The newest version of the Cadence Allegro platform has been selected by Tektronix as our primary analog/mixed-mode ASIC, packaging, and PCB development tool suite," said Bart Welling, director of Engineering Tools, Tektronix. "The new functionalities of the Allegro platform reduce prototype turns, enabling a constraint-driven design flow from the very beginning at our engineers' desktops."
New constraints across Allegro platform products are able to account for critical signal delays inherent in IC packages and vias. These new constraints eliminate the time-consuming need for designers to link to the package database or manually account for these critical signal delays, allowing engineers more flexibility and enabling increased accuracy during the design process.
A key product in the latest Allegro platform release, the Allegro(R) Design Entry HDL, provides front-end support for the creation and simulation of equivalent extended nets in design entry. The Allegro(R) Design Entry HDL product helps enhance productivity through improved page management operations and improved constraint application across signal nets.
This release also introduces new features and technologies for the Allegro platform's Allegro(R) PCB Editor, the Allegro(R) PCB SI and the Allegro(R) Constraint Manager. The Allegro(R) PCB Editor adds UNDO/REDO capability and interactive etch tuning functionality that provides real-time feedback. The Allegro(R) PCB SI adds improvements for ease of use, support for IBIS 4.0, integration with a 3D field solver for package design, and support for new rules which can shorten post layout verification time. Finally, Allegro(R) Constraint Manager can boost productivity with a new properties worksheet and usability improvements.
"The Allegro platform version 15.2 provides engineers with a whole new level of easy-to-use design flow capabilities," said AJ Incorvaia, group director for the silicon-package-board business unit at Cadence. "Our aim is to continue our leadership and innovation in silicon-package-board design technology and bring shortened design cycle times to the engineering community through our unique constraint-driven design flows."
Cadence is the largest supplier of electronic design technologies and engineering services. Cadence solutions are used to accelerate and manage the design of semiconductors, computer systems, networking and telecommunications equipment, consumer electronics, and a variety of other electronics-based products. With approximately 4,800 employees and 2003 revenues of approximately $1.1 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com.
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