FREMONT, Calif., May 28, 2014 -- ClioSoft Inc., a leader in hardware configuration management (HCM) solutions for the semiconductor design industry, will demonstrate the SOS design collaboration platform and present in the IP Track at DAC 2014. SOS from ClioSoft provides IP and design data management for global design teams and is seamlessly integrated into all major digital, analog/mixed-signal, RF and custom IC design flows.
The IP Track at the 51st DAC focuses on the latest developments and approaches to IP quality. Real world examples will illustrate how methodology, design management, verification, and metrics can lead to better, more reliable products.
WHAT: ClioSoft will present on “Managing Designs to Produce High-quality PHY IPs.” Abstract: As IP design complexity has increased significantly, so has the number of engineers involved in completing an analog IP design. While RTL and verification teams have long used design management software, including open source choices, the analog design world has been slow to adapt. Using a design management solution coupled with a well-defined design and verification methodology enabled by automation is a necessity to ensure the quality and delivery schedule of a PHY IP. This presentation highlights the issue of managing the design process to improve the quality of the IP produced, with a focus on design management.
WHEN: The Verification topic area of the IP Track takes place from 10:30am – 12:00 noon on Monday, June 2, 2014.
WHO: Amit Varde, Applications and Support Manager at ClioSoft, will present on information authored by ClioSoft and by Ritesh Saraf and Claude Gauthier of OmniPhy.
WHERE: Room 101, Moscone Center, San Francisco, CA.
WHAT: The SOS platform from ClioSoft provides the essential infrastructure that enables designers across multiple sites to share data accurately and work more efficiently. Revision control, release and derivative management, IP management, and issue tracking streamline the design and reuse process. Tight integration with the major design flows improves design team productivity by providing data management and tool features from the same cockpit, helping to reduce the possibility of design re-spins due to incorrect configurations.
Visual Design Diff (VDD) from ClioSoft gives users the power to quickly compare two versions of a schematic or layout by graphically highlighting the differences directly in their own design editor. A hierarchical option allows all differences for the entire design hierarchy to be flagged.
WHEN: 9:00am to 6:00pm Pacific from Monday, June 2 to Wednesday, June 4, 2014. Register at www.cliosoft.com/dac to arrange a private demonstration.
WHO: Of interest to analog/mixed-signal designers, digital designers and CAD engineers/ managers.
WHERE: Booth #2425, Moscone Center, San Francisco, CA.
ClioSoft is the premier developer of hardware configuration management (HCM) solutions for analog/ mixed-signal and digital designs. The company's SOS Design Collaboration platform is built to handle the complex requirements of system-on-chip (digital, analog, mixed-signal) design flows. The SOS platform provides a sophisticated multi-site development environment that enables global team collaboration, design data management, IP management, and reuse and efficient management of design data from concept through tape-out. SOS is integrated with leading design flows – Agilent’s Advanced Design System (ADS), Cadence’s Virtuoso® Custom IC, Mentor Graphic’s Pyxis Custom IC Design, Synopsys Galaxy Custom Designer® and Laker3™ Custom Design.
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