Verific to Demonstrate Enhancements to UPFParser During DVCon

SystemVerilog, VHDL Parser Platforms to be Presented

ALAMEDA, CALIF. –– February 19, 2014 –– WHO: Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog, VHDL and UPF parsers,

WHAT: Will demonstrate enhancements to its parser for the IEEE 1801-2013 Universal Power Format (UPF 2.1) standard for the design and verification of low-power integrated circuits at DVCon 2014 in Booth #805. The UPF parser is an integral component of Verific’s Parser Platform and interacts seamlessly with Verific’s standard SystemVerilog and VHDL parsers that will be demonstrated as well.

WHEN: Monday, March 3, from 5 p.m. until 7 p.m., Tuesday and Wednesday, March 4-5, from 2:30 p.m. until 6 p.m.

WHERE: Doubletree Hotel in San Jose, Calif.

Information about Verific can be found at: www.verific.com.

TheDVConwebsite is located at: www.dvcon.org.

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.      


Contact: 

Nanette Collins
Public Relations for Verific
(617) 437-1822
Email Contact




Review Article Be the first to review this article

ALDEC:

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Reverie: All That Glitters is not Past
More Editorial  
Jobs
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
SoC Design Engineer for Intel at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Senior Physical Design Engineer for Ambiq Micro at Austin, TX
Technical Marketing Manager Valley for EDA Careers at San Jose, CA
Digital and FPGA Hardware Designer for Giga-tronics Incorporated at San Ramon, CA
Upcoming Events
European 3D Summit 2017 at 3, parvis Louis Néel 38054 Grenoble France - Jan 23 - 25, 2017
3D Printing Electronics Conference at High Tech Campus 1, 5656 Eindhoven Eindhoven Netherlands - Jan 24, 2017
DesignCon 2017 at Santa Clara Convention Center Santa Clara CA - Jan 31 - 2, 2017
Embedded Neural Network Summit at San Jose CA - Feb 1, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy