Verific to Demonstrate Enhancements to UPFParser During DVCon

SystemVerilog, VHDL Parser Platforms to be Presented

ALAMEDA, CALIF. –– February 19, 2014 –– WHO: Verific Design Automation, supplier of industry-standard, IEEE-compliant SystemVerilog, VHDL and UPF parsers,

WHAT: Will demonstrate enhancements to its parser for the IEEE 1801-2013 Universal Power Format (UPF 2.1) standard for the design and verification of low-power integrated circuits at DVCon 2014 in Booth #805. The UPF parser is an integral component of Verific’s Parser Platform and interacts seamlessly with Verific’s standard SystemVerilog and VHDL parsers that will be demonstrated as well.

WHEN: Monday, March 3, from 5 p.m. until 7 p.m., Tuesday and Wednesday, March 4-5, from 2:30 p.m. until 6 p.m.

WHERE: Doubletree Hotel in San Jose, Calif.

Information about Verific can be found at:

TheDVConwebsite is located at:

About Verific Design Automation

Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 60,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website:      


Nanette Collins
Public Relations for Verific
(617) 437-1822
Email Contact

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