Offers Giga-scale Capacity, Enhanced Speed, Analysis, and Language Support
SUNNYVALE, Calif. – Jun. 18, 2013 – Real Intent, Inc., a leading provider of EDA advanced sign-off verification solutions, today announced the Version 5.0 release of its Meridian CDC product for comprehensive clock domain crossing analysis. This new software release adds enhanced speed, analysis and SystemVerilog language support, maintaining Real Intent’s product leadership in delivering what the company believes is the industry’s fastest-performance, highest-capacity and most precise CDC solution in the market.
Meridian CDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC or FPGA devices are received reliably. With a giga-scale capacity, Meridian CDC is the only solution that enables all aspects of CDC sign-off. Meridian CDC excels in speed and low-noise analysis of asynchronous clock domains in SoC designs, with an enhanced formal engine that now goes even further and faster to find hidden CDC problems. Its design language support now includes the SystemVerilog synthesizable subset. In addition, Real Intent has substantially enhanced the user experience with a new front-end interface that incorporates the latest Verdi Automated Debug System from Synopsys, and delivers improved analysis setup, debug features and ease of use.
New features of Meridian CDC Version 5.0 include:
- A hierarchical flow that supports partitioned analysis of designs without waivers or sacrifice of top-level full-chip precision to achieve sign-off of giga-scale designs
- A new correct-by-configuration design setup to enhance analysis and reporting clarity for clock crossings to ease the sign-off process
- Enriched SDC design constraint support with the addition of set clock groups and naming schemes
- “Cleaner and meaner” issue reporting for: bus handling; reset analysis, including glitches in both asynchronous and synchronous domains; and crossings that may be blocked by environment definition
- An enhanced formal analysis engine with greater speed and coverage
- Significant enhancements to the SystemVerilog support for interface elements
- Verdi3 integration - the industry-leading debug platform from Synopsys (formerly SpringSoft)
Sarath Kirihennedige, senior manager of product engineering at Real Intent, said, “Our new hierarchical CDC flow supports partitioned analysis of designs without sacrificing top-level full-chip precision for giga-scale sign-off. Other legacy solutions in the marketplace try to offer a high-capacity gate solution, but sacrifice coverage and analysis accuracy to get it. Meridian CDC’s hierarchical flow avoids the compromises found with abstract-modeling and the use of waivers in other products.” For additional comments from Sarath, please watch a video interview here.
The new release of Meridian CDC is available in August, 2013. Pricing depends on product configuration. For more information, please email email@example.com.
About Real Intent
Companies worldwide rely on Real Intent’s EDA software to accelerate early functional verification and advanced sign-off of electronic designs. The company provides comprehensive CDC verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. Real Intent’s Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness. Please visit www.realintent.com for more information.
ASIC: Application-Specific Integrated Circuit
CDC: Clock Domain Crossing
EDA: Electronic Design Automation
FPGA: Field-Programmable Gate Array
RTL: Register Transfer Level
SDC: Synopsys Design Constraints
Ascent and Meridian are trademarks of Real Intent, Inc.
All other trademarks and trade names are the property of their respective owners.
Sarah Miller for Real Intent
ThinkBold Corporate Communications