Media Alert: Kilopass to Present Non-Volatile Memory IP Roadmap for TSMC Process Technologies During 50th Design Automation Conference

SANTA CLARA, CA -- (Marketwired) -- May 24, 2013 --
WHO:
Bernard Stamme, Director of Marketing and Applications for Kilopass Technology Inc. ( www.kilopass.com), the leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP)

WHAT:
Will present the roadmap for Kilopass' one-time programmable (OTP) NVP memory IP and enablement down to TSMC 20-nanometer process technology at the 50th Design Automation Conference (DAC) in the TSMC Booth #1746

WHEN:
Monday, June 3, from noon until 12:10 p.m.; Tuesday, June 4, from 1:30 p.m. until 1:40 p.m. and Wednesday, June 5, from 10:30 a.m. until 10:40 a.m.

WHERE:
The Austin Convention Center in Austin, Texas
Details about Kilopass and its semiconductor logic NVM IP can be found at: www.kilopass.com.
For information on TSMC, visit: www.tsmc.com.

About Kilopass
Kilopass Technology Inc., a leading supplier of embedded NVM intellectual property, leverages standard logic CMOS processes to deliver one-time programmable (OTP) and many-time programmable (MTP) memory. With 58 patents granted or pending and more than 800,000 wafers shipped from a dozen foundries and Integrated Device Manufacturers (IDMs), Kilopass has more than 150 customers in applications ranging from storage of firmware and security codes to calibration data and other application-critical information. The company is headquartered in Santa Clara, Calif. For more information, visit www.kilopass.com or email Email Contact. Follow Kilopass on Twitter at https://twitter.com/kilopass_.

Gusto, Gusto-2, Numera, XPM and XPM Xtend are trademarks of Kilopass Technology Inc. All other tradenames and trademarks are the property of their respective holders.

For more information, contact:
Nanette Collins 
Public Relations for Kilopass Technology 
(617) 437-1822 

Email Contact 

Jonah McLeod
Kilopass Technology
(408) 980-8808 x130

Email Contact 





Review Article Be the first to review this article
Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Job Openings: Can EDA Predict the Future
More Editorial  
Jobs
ASIC Design Engineer for Ambarella at Santa Clara, CA
Senior FPGA Designer for Fidus Electronic Product Development at Fremont, CA
Timing Design Engineer(Job Number: 17001757) for Global Foundaries at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Verification Engineer for Ambarella at Santa Clara, CA
ASIC Design Engineer 2 for Ambarella at Santa Clara, CA
Upcoming Events
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017
10th Anniversary of Cyber-Physical Systems Week at Pittsburgh, PA, USA PA - Apr 18 - 21, 2017
DVCon 2017 China, April 19, 2017, Parkyard Hotel Shanghai, China at Parkyard Hotel Shanghai Shanghai China - Apr 19, 2017
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy