March 06, 2013
EdXact, provider of advanced software solutions that accelerate post layout design and verification is going to exhibit as a technical partner at the Designer Expo at CDNLive Silicon Valley next week.
EdXact will exhibit its product families that have been build on a common analysis platform Alps™.
- Jivaro™, EdXact's netlist reduction engine allows to reduce the overhead of interconnect parasitic components on circuit simulation time with a very high degree of accuracy and efficiency. Jivaro has several tight links at different places in the design environment of Cadence.
- Viso™, EdXact's circuit analysis tool provides fast analysis capabilities to the designer. Quickly verifying the resistance between ports, determining the cross-coupling between nets, estimating the delay, fast calculation of RdsOn for large embedded PowerMOS devices, are the tasks Viso solves on a daily basis.
- Belledonne™, EdXact's circuit comparison tool with emphasis on parasitics allows to compare quickly and accurately very large netlists in order to tune parameters of extraction tools, find differences between two versions of a design, increase robustness of design kits.
CDNLive Silicon Valley brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
Founded in 2004, EdXact focuses on electronic design tools aimed at physical verification tasks. EdXact’s innovative model order reduction technology helps to accelerate extensive backend verifications in complex IC design cycles. EdXact is headquartered in Grenoble area, France with local sales offices in California, Japan, Korea and Taiwan.
For additional information please visit: http://www.edxact.com
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