Aldec Launches Free Online UVM Training

HENDERSON, Nev. — (BUSINESS WIRE) — February 4, 2013Aldec, Inc. today announces the launch of Fast Track™ ONLINE, a convenient, online training portal that is available at no cost to the design verification community. In today’s competitive atmosphere, the ability to adopt new technology quickly and reduce design time cycles is critical. As a global industry leader, Aldec is committed to offering educational opportunities and resources to help busy engineers get up to speed quickly.

“Engineers from locations around the world now have access to world-class technical training – at no cost,” said Jerry Kaczynski, Aldec Research Engineer and contributor to the Fast Track™ training curriculum. “These private, online trainings will allow the user to go through each module at their own pace, and even go back to review material. Each individual module also offers a quick self-test to ensure the module is grasped before proceeding.”

The premier training course for the new program is ‘Fast Track™ to UVM ONLINE’, taken directly from Aldec’s most popular onsite training curriculum:

Fast Track™ to UVM ONLINE

This course introduces hardware designers familiar with Design Subset of SystemVerilog into the brave, new world of Universal Verification Methodology (UVM).

Typical hardware designers may not be responsible for maintaining the complete verification suite of large system-level designs, however they often work with verification engineers while creating these environments. For this reason, ‘Fast Track™ to UVM’ begins with an introduction, or refresher, of SystemVerilog constructs used in UVM (classes, objects, randomization, coverage, interfaces), provides outline of TLM, discusses general structure of UVM, and progresses to more a detailed description of verification components and their usage.


This convenient, online training portal is available at no cost to all registered users. Signing up for an Aldec account is easy and provides one-click access to event registration, support, product downloads, evaluation licenses, recorded webinars, white papers, application notes and other resources. To get started, visit

About Aldec

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.

Aldec is a registered trademark of Aldec, Inc. All other trademarks or registered trademarks are the property of their respective owners.


Aldec, Inc.
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