Verific Design Automation Increases Revenue by 20% in 2012

ALAMEDA, CA -- (Marketwire) -- Jan 28, 2013 -- Verific Design Automation (, provider of SystemVerilog, Verilog and VHDL parsers, ended 2012 with 52 active user companies and a revenue increase of 20% over 2011.

"Much of our business in 2012 came as a result of our reputation for quality, reliable software and excellent customer service, the hallmarks of our corporate culture," says Michiel Ligthart, Verific's president and chief operating officer. "EDA developers continue to select our parsers so that they can focus on their core competencies and get their products to market more efficiently."

In 2012, Verific signed six new licensed customers in a mix that includes both electronic design automation (EDA) companies and integrated device manufacturers (IDMs). Several existing customers added further software to their existing product mix.

Verific's software serves as the front end to a wide range of EDA and field programmable gate array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of register transfer level (RTL) designs. The Verific Parser Platform includes support for SystemVerilog, Verilog, VHDL and UPF, and provides C++ and Perl application programming interfaces (APIs). Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux and Windows operating systems.

About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides parsers and elaborators for SystemVerilog, Verilog and VHDL. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website:

Verific Design Automation acknowledges trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822

Email Contact 

Review Article Be the first to review this article

Featured Video
Principle Electronic Design Engr for Cypress Semiconductor at San Jose, California
Applications Engineer for intersil at Palm Bay, Florida
Design Verification Engineer for intersil at Morrisville, North Carolina
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
NVIDIA’s GPU Technology Conference (GTC) at San Jose McEnery Convention Center 150 West San Carlos Street San Jose CA - Mar 26 - 29, 2018
ESC Conference Boston at boston MA - Apr 18 - 19, 2018
IEEE Women in Engineering International Leadership Conference at 150 W San Carlos St San Jose CA - May 21 - 22, 2018
DownStream: Solutions for Post Processing PCB Designs

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise