True Circuits Attends Design Automation Conference

Showcases Complete Line of Silicon Proven 28nm Analog PLL and DLL IP

June 4-6, 2012, Moscone Convention Center, Booth #2726

(BUSINESS WIRE) — June 4, 2012 — True Circuits, Inc.:

Who
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries.

What
At the Design Automation Conference (DAC), True Circuits will feature its complete line of standardized clock generator, spread spectrum, deskew, low bandwidth, and general purpose PLLs and multi-slave and multi-phase DLLs that spans nearly all performance points, features and foundry processes typically requested by ASIC, FPGA and SoC designers for core clocking, DDR, SerDes and audio/video applications.

True Circuits will showcase its complete line of PLL and DLL IP for TSMC and GlobalFoundries 28nm processes and discuss the extensive parametric testing process used to silicon validate comprehensive IP test chips completed in each 28nm process flavor. We will also discuss a number of topics that should be helpful to chip managers and designers, including IP selection, IP integration, IP reuse, jitter specifications and silicon testing.

Stephen Maneatis, True Circuits' CEO, John Maneatis, Ph.D., True Circuits' President and Brian Gardner, True Circuits' V.P. of Business Development, will also make presentations about True Circuits and our latest timing IP in the ChipEstimate.com booth #1202 and the TSMC OIP booth #2430 each day of the conference.

When and Where

Moscone Convention Center, San Francisco, CA
 
True Circuits Booth #2726
Monday - Wednesday, June 4-6, 9:00 AM to 6:00 PM
 
ChipEstimate.com Booth #1202
Monday, June 4, 11:00 AM
Tuesday, June 5, 2:00 PM
Wednesday, June 6, 2:00 PM
 
TSMC OIP Booth #2430
Monday, June 4, 11:15 AM
Tuesday, June 5, 4:00 PM
Wednesday, June 6, 11:30 AM
 

Contacts

For more information about True Circuits' PLLs and DLLs, please visit www.truecircuits.com.

For more information about the Design Automation Conference, please visit www.dac.com .

 

1 | 2  Next Page »



Review Article Be the first to review this article
Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Fall Schedule: A Host of Must-attends
More Editorial  
Jobs
Senior Methodology Automation Engineer for EDA Careers at San Jose, CA
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Proposal Support Coordinator for Keystone Aerial Surveys at Philadelphia, PA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
The Rise of Mechatronics at Dassault Systèmes San Diego 5005 Wateridge Vista Drive San Diego CA - Sep 12, 2017
The Rise of Mechatronics at Buca di Beppo - Pasadena 80 West Green Street Pasadena CA - Sep 13, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy