EdXact Demonstrates New LPE Flow Qualification Tool Belledonne at DAC 2012

Belledonne allows to quantitatively judge on quality of LPE tools

San Francisco, CA and Grenoble, France --  Backend verification specialist EdXact SA today announces the availability of Belledonne™, an industry first solution for the qualification of LPE tools. Belledonne allows providers of PDK (process design kits), CAD tool integrators and designers to accelerate the creation, update and delivery of PDK and post-layout verification flows, by using a powerful measure for the accuracy of any LPE tool.

LPE, layout parasitics extraction, is an area in EDA under heavy development. Moving to modern process nodes and smaller feature sizes, the impact of the layout parasitics is getting a dominant woe, requiring more accurate extraction methodologies. The process of qualifying LPE tools and choosing the correct options in order to trade off between accuracy and performance of the downstream tools is a task, that has not been addressed by an industrial tool on large-scale data until today.

Belledonne has been developed as a neutral measuring instrument, that analyzes quantitatively the accuracy of post-layout netlists generated by LPE tools. Belledonne reads two netlists in DSPF, SPEF, Spice or Spectre format and compares different metrics, such as the effective resistance or the effective RC delay between thousands of pins.

Belledonne can be run in batch-mode and is integrated into EdXact's Parasitics Analysis Platform Alps™. The platform has been designed with the observation, that layout parasitics need dedicated and smart analysis at advanced design nodes. The underlying mathematical database allows for very fast and accurate analyses.

About DAC 2012

The Design Automation Conference 2012 is being held in San Francisco, June 4-6 at Moscone Convention Center. EdXact can be visited in Booth 1002.

About EdXact

Founded in 2004, EdXact SA focuses on electronic design tools aimed at physical verification tasks. EdXact’s innovative model order reduction technology helps to accelerate extensive backend verifications in complex IC design cycles. EdXact is headquartered in Grenoble area, France with sales offices in Japan, Korea and Taiwan.

For additional information: http://www.edxact.com or mail contact: Email Contact




Review Article Be the first to review this article

Aldec Simulator Evaluate Now

Featured Video
Jobs
Design Verification Engineer for Cirrus Logic, Inc. at Austin, TX
RF IC Design Engineering Manager for Intel at Santa Clara, CA
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Upcoming Events
IC Open Innovation Panel During REUSE 2017 at Santa Clara Convention Center 5001 Great America Parkway Santa Clara CA - Dec 14, 2017
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise