Morning at the Oasys
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Morning at the Oasys


This is the May 07, 2012 article for the EDA Commentary. The article is entitled, “Morning at the Oasys.”  

About six months into 2011, having been the author of both the quarterly EDA Commentary for 8 years and the monthly EDA WEEKLY for some 19 months, and having done in-depth profiles of many EDA, IP and MCAD/MCAE vendors in previous articles, your writer decided to begin the process of scheduling an interview with Rajeev Madhavan, then the colorful CHAIRMAN of MAGMA Design Automation. Our preparatory interactions went as far as obtaining from Rajeev his answers to our starter BIO Questionnaire as well as scoring a series of candid photographs of the MAGMA Chairman in action. 

During the summer and early autumn of 2011, dates for the actual interview with Rajeev were repeatedly set, only to be delayed by schedule conflicts on the parts of one or both parties.

Next came the surprise announcement in late 2011 that Synopsys planned to acquire MAGMA. This is when your writer set aside further pursuit of the Madhavan interview idea, in favor of a kind offer from one Nanette Collins [1] to stay close to the evolving Synopsys-MAGMA story and perhaps eventually resurrect the opportunity for an EDA WEEKLY MAGMA-related article.

Exit MAGMA, Hello Oasys

Alas, once the acquisition of MAGMA was finally consummated in February 2012, and MAGMA disappeared into Synopsys, so did our Rajeev Madhavan story interest [2].

But that merger also meant that there remained fewer EDA companies in the marketplace offering synthesis technology for teams designing SoCs. That is, just Synopsys and Cadence seemed to remain in the minds of many folks (for synthesis).

 “Ah, let’s not forget that private company that our friend Joe Costello [3] is now affiliated with,” said your writer, referring of course to the still private company based in Silicon Valley, Oasys Design Systems.

At that point in the discussion,  Nanette revealed that she had been involved in some Public Relations work for Oasys and that she knew Paul van Besouw, the founder and CEO of Oasys. Busy with several other pressing tasks, the writer asked Nanette to follow up with Oasys.

Shortly thereafter, Nanette booked an appointment with Paul van Besouw and took a trip over to San Tomas Expressway and 101 in Santa Clara, in many people’s minds the geographic epicenter of Silicon Valley. Nanette subsequently offered an interview record of her first meeting with Oasys on behalf of the EDA WEEKLY [4].

Somewhat later a second interview occurred. The two interviews were recently combined and the result is given below.

The Combined Interview with Oasys

Paul, please tell us about your background.

“I was born and reared in the Netherlands. I am one of the founders of Oasys, along with Johnson Limqueco, vice president of R&D, and Harm Arts, who is also from the Netherlands as it happens. Harm is our CTO [5].

We were all part of the original R&D team at Ambit Design Systems that was acquired by Cadence over a decade ago.  At Cadence, the team focused on physical synthesis, connecting traditional synthesis to physical design.

             Oasys founders, from left to right, Harm Arts, Paul van Besouw and Johnson Limqueco.


I have a Master of Science degree in Electrical and Computer Engineering from the Eindhoven University of Technology in The Netherlands.  My start in the EDA industry goes back to when I was at the university.  I was part of a group doing EDA research. Rajeev Madhavan, who was then starting Ambit, emailed me that he needed software developers who had experience developing RTL synthesis front-ends.  I was just finishing my master’s degree, so the timing was perfect. That was 1995.  I talked to Rajeev and he invited me to visit to California.  I packed my bags and came over, and that is how the whole thing started.  It was initially meant to be a six-month assignment and it’s now over 15 years.

Just coming out of university with no industrial experience, it was a great opportunity. We had to build everything from scratch. With a core team of only six people, we built the foundation of the Ambit technology.

You were at Cadence and you decided to quit and start Oasys?  What motivated that?

By building synthesis technology at Ambit and separately building physical technology at Cadence, we realized that we had created a suboptimal solution, and then were forcing design teams to deal with it.  It is really hard to integrate two separate products, a synthesis product and a place and route product into one and get the best design results.  We knew there had to be a better way.

All synthesis tools before Oasys’ RealTime Designer basically went naively from RTL to gates and then threw the gates into optimizers with some level of physical knowledge.  But the initial netlist was often so far from what was needed, that it took an incredible amount of time to get close to closing timing.

In traditional synthesis tools, the “integration” was being done at the gate level.  This level of integration really didn’t address the fundamental problem –– the fact that the choices you made during RTL synthesis determine the quality of results after place and route. 

Since there was no physical information during RTL synthesis, there really wasn’t a way to make the right choice.  That triggered a question about how it should really be done –– can you build a tool that produces better quality if you combine RTL synthesis and physical synthesis in a single engine?  The answer was not obvious, but we concluded that there should be.

We started Oasys, and tried to figure out how to go from RTL to placed gates in a way where there is much better conversion to physical design.  It took the team two years to build a new technology from scratch. The first prototype solution was qualified on an actual customer design.  The designers reactions were priceless.  After they verified the design and validated the quality of results on site, the design team leader said:  “Wow! The run really did take less than 15 minutes!”

Traditional synthesis turns RTL code into a quick-and-dirty netlist and then runs a powerful but slow optimizer on that netlist.  OASYS’ goal is to produce the best starting point for physical implementation by producing placed netlists that in turn enable the place and route tool to deliver the targeted quality of results.  We put a lot of effort up front to intelligently turn RTL code directly into placed gates, or what we call Chip Synthesis technology.  When the timing doesn’t close, we don’t optimize the gates, we go back to the RTL level and re-synthesize, repartition and re-place part of the design.

Last year, we added DFT capabilities to RealTime Designer, for designers to create a better DFT architecture and chip partitioning.  Full-chip DFT synthesis can be performed in a single pass with fast turnaround and without the need for complex DFT abstraction and bottom-up flows.


         The team that built RealTime Designer at the Oasys’ Olcott Street in Santa Clara, CA.


So where is Oasys today?

I’m pleased to tell you that we recently closed Series B Funding with investments from Intel Capital, Intel’s global investment organization, and from Xilinx, a leading provider of programmable platforms [6].  We plan to use the funding as working capital to expand our research and development team, and our worldwide support structure.

Wow. Two industry giants Intel and Xilinx have invested in Oasys! That portends good things, doesn’t it?

We haven’t been too visible recently as we focused inwardly, but we were certainly not inactive and we now have several customer design teams using RealTime Designer on real designs. Our customers are ‘the numbers two through four’ semiconductor companies, namely Texas Instruments, Qualcomm and Broadcom (through the Netlogic acquisition). Xilinx, the number 1 FPGA vendor, is a customer. Now with Intel, we have relationships with the top four U.S. semiconductor vendors and the top FPGA vendor, all of whom are doing some of the most advanced designs today.

Let me provide a bit more detail. Not all of our customers let us use their names, of course, but I can assure your readers that we have a pretty impressive customer list of industry leaders designing some of the most aggressive IP and SoCs –– large and with high-performance and low-power constraints that make them challenging. And, we have an impressive funnel of other potential customers evaluating the technology. 

While I’m on the subject of sales, two key members of the Oasys team are Craig Robbins and Bunninder Falak, both well-liked and experienced EDA sales giants.  Craig is senior vice president of sales, while Bunninder is our vice president of business development.  Together, they have built an impressive and dedicated customer support and service organization that we’re quite proud of.

Key members of the Oasys Sakes team: Bunninder Falak (left) and Craig Robbins (right).


 Can you share Oasys’ elevator pitch?

Sure. “Oasys software tools eliminate unending design closure iterations between synthesis and layout. Our Chip Synthesis is a fundamental shift in how synthesis is applied to IC design and implementation. From our perspective, traditional block-level synthesis tools do a poor job of handling chip-level issues. We built RealTime Designer for physical RTL synthesis of 100-million gate designs to produce better results in a fraction of the time needed by traditional logic synthesis products. We eliminate iteration through a unique RTL placement.” 

Impressive! What are some other things you have learned?

The team is the most important thing.  I’ve run teams in bigger companies and there is inevitably a certain amount of bureaucracy.  To be successful in a big company, you have to execute well on your little piece of the puzzle without necessarily looking at the big picture.  In a startup, especially in the early days, you need to have everyone pulling in the same direction.  Everyone really does need to know what everyone else is doing, at least in outline.  And, that’s what we strive to do at Oasys.

Of course, we started the company at a terrible time from the point of view of raising money, so we didn’t raise a large amount of funding early on.  But that has turned out to be a blessing.  We’ve had to take our time with a group of patient smaller investors.

Six years was not what we envisioned, but the reality is, that I don’t think we could have done anything differently.

Obviously, with more funding, we might have been able to speed up the product development.  However, the lack of funding forced the team to focus on building a solution that customers would buy, rather than aiming for an all-encompassing product.  This led to several successful engagements, and helped us in closing some significant business before the product was even complete.  It allowed us to bootstrap the company in a different way, and gave us an alternative route to traditional venture capital funding.  The fact we did not rely on VC funding definitely turned out to be in our favor in the end.

What do you take the most pride in or satisfaction from?

We created a new technology with a small team and little funding.  At first, we were completely self-funded.  We rented a small apartment where we spent about a year just coding everything from scratch.  Later, we received some seed funding from several EDA-savvy angel investors, which allowed us to move into a “real” office.

We had a working prototype by 18 months to show other angel investors, and that step allowed us to secure a bit more funding.  I was then able to attract interest from some of the best people in the industry.  It took some convincing, but I was able to attract Joe Costello’s attention.  He is now a member of our board of directors and a key contributor to our team.


Joe Costello

Joe’s keynote speech at the Design Automation Conference several years ago resonated with me and others at Oasys.  He talked about the three rules to building a successful company in EDA.  The rules describe about how to “think like a fish,” and that you should “write your press release first,” and to “fundamentally change the rules.”  That was around the same time that I started my discussion with Joe.  I talked him through the technology and how we did things.  He definitely saw the potential of this kind of technology where it could fundamentally change the game rather than just trying to play the game, which is basically what we had done at Ambit.

And, in case you missed it, Joe was a member of our band, the Chip Synthesis Revolution Rockers, that performed for a video and CD that became a hot DAC giveaway in 2009.  The video featuring Bass ‘n Vocal Rocker Joe Costello can be found on the Oasys website (

I should also mention that Gary Meyers is a member of our board.  He was president and CEO of Synplicity, a synthesis company acquired by Synopsys.  After the acquisition, he became vice president and general manager.  Another board member is Larry Yoshida, chairman and CEO of Premier Technologies.

Gary Meyers, former president and CEO of Synplicity, now part of Synopsys, is a member of the Oasys board; he also serves on the Mentor Graphics board

Larry Yoshida is chairman and CEO of Premier Technologies and a member of the Oasys board.

One other thing to mention is the sheer speed of RealTime Designer.  We started with the goal to design a product that used this new RTL-savvy approach to produce the best possible results.  We were as surprised as everyone else when it turns out that, not only does it produce better results, but also it typically runs between 10 and 60 times faster than traditional synthesis.  We’ve had AE’s finish an evaluation in an afternoon.  Huge designs just load and are done in minutes or a few hours.

You’ve talked a lot about “timing” and “RTL” but these days it seems that “power” is one of the big issues. What are you capabilities there?

Yes, power is a huge issue and one of the challenges is that power is mostly a chip level problem.  Design teams care about how long the battery will last in a phone, system engineers care about whether they can get away with a cheap package, avoid a fan, and so on.  Nobody cares really about how much power individual blocks take, apart from perhaps some local thermal issues.  It is a weakness of traditional tools that the power budget has to be divvied up without really any rationale for how to do it.

We operate at the chip level, which means we can handle power at the chip level and make tradeoffs across the whole design.  It is easy to change the value of some islands and re-synthesize the entire design in a few minutes and immediately see the results.  With a traditional approach that might take a week of work.  In practice, the early traditional power budgets got cast in stone since they were so difficult to change, which can then lead to last-minute crises when some of them turn out to be impossible to meet.

What has been Oasys’ biggest challenge?

(This was where we could really see Paul warming to his reply):

“We are competing in a mature market, in the sense that everyone already has a tool that does something similar to what we do.  We have to deliver a solution that is as reliable as the competition and fits into existing flows before anyone even considers whether our results are better.

That was a lesson we learned back at Ambit.  If your netlist is not correct, nobody cares about the performance.  If you can’t read the library correctly, you don’t get to compete.

Another challenge is making it so that the technology is easy to adopt. Synthesis sits at the heart of everyone’s design flow, not in a little niche that only a couple of experts need to concern themselves with. So making RealTime Designer as painless as possible to get started with has been very important, as does having a team of superb AE’s to train customers and to cope with the inevitable issues that come up as the tool matures.

The investment environment has had an obvious impact.  Venture capital for EDA is pretty much non-existent (these days) and I don’t think that is suddenly going to change.  It’s a new reality and we were forced to do things differently.  As a result, we are working with less than we would have if we had started Oasys 10 years ago.  Magma and Monterey both raised around $100 million in venture capital, and that is not going to happen again.  We would never have needed that amount of capital, but even relatively small amounts of VC money are impossible today.  That means less money, fewer engineers and a longer development time-line.

Nobody embarks on a startup thinking it’s a six-year endeavor just to get to market, but that’s the reality we faced.  On the other hand, it did allow us to focus on maturing the product before announcing the product and/or company.

When we started, we had a different perception than we have now.  With my background from Ambit, I knew what it would take to build things from scratch, but we were still counting on the funding to be there.  In the end, scarce funding was actually a blessing because we were forced to do more with less.  It was a core team that worked on the technology from the ground up rather than having some ideas, build something and then have a big team work it out.  In the end, it has helped the technology mature in the way it did because it was a technology completely different from what we had ever done before. There is a lot of satisfaction that comes from working with a small team of very knowledgeable and productive engineers.

However, it definitely took longer to develop the technology because of a lack of funding.  It took us three years to get to a point where we could start engaging with some design teams.  However, when we did, we realized that we had something different that was even better than we had imagined.

We started with a focus on how to combine RTL and gate-level synthesis in a unique way that basically gets better quality results.  As we put this technology together, we realized that working on a higher level of abstraction was the right thing to do.  Making these decisions much earlier at RTL is the way to go rather than going down to a gate-level netlist and doing a lot of lower level optimization.  The speedup we got with that approach and how we built out the technology allowed us to run much bigger blocks, bigger designs and get the quality results we were looking for.

I don’t want to imply that the challenges are behind us.  Our biggest challenge today is probably that we need to support all our initial customers and make them successful.  This requires our AEs and our engineering team to be responsive.  It is critical that we don’t take on customers faster than we can make them successful. 

You never get a second chance to make a (good) first impression; that quote is attributed to both Irish writer and poet Oscar Wilde and American humorist Will Rogers, and it readily applies to EDA.  In this industry, companies get only one chance to show that their tool is something that a mission-critical design can use.

With the new investment from Intel Capital and Xilinx, our focus today is to continue to build success in the marketplace through solid engagements with customer design teams and get our technology adopted in their production flows.” 

A perfect place to end a great interview!




[1] The writer first become acquainted with Nanette Collins telephonically in 2010 when she worked with Lauro Rizzatti of EVE on one of the early EDA WEEKLY interviews the writer did with the founder of EVE’s North American office in San Jose, CA.

Later, Nanette was instrumental in encouraging Lin Hong and Jonah McLeod of Kilopass Technology to submit the first guest article in the January 10, 2012 EDA WEEKLY, while the latter was otherwise devoted to “Blurring the line between EDA and Test.”

The Kilopass guest article was entitled, “Building a Successful Non Volatile Memory (NVM) Company on the basis of CMOS Oxide Breakdown.”

Subsequently, Nanette assisted in obtaining Breker Verification Systems’ participation in the more recent EDA WEEKLY posting of February 06, 2012 entitled, ”Silicon Valley – EDA Magnet,” in a similar role that Georgia Marszalek played in helping to gain the cooperation of Silicon Frontline for the same two-part article penned by yours truly:

[2] Readers who are interested in what Rajeev Madhavan is up to these days, may want to see Peggy AycInana’s recent interview with Rajeev:

[3] That Oasys was pursuing the synthesis business and that Joe Costello was a board member represented the entire, then-current extent of the writer’s familiarity with Oasys at that moment. Of course, the writer knew and admired Joe Costello, as the writer had run a division of Mentor Graphics for four years in Silicon Valley while Joe was the charismatic CEO of MGC-arch rival Cadence; then the writer had transferred to Oregon to turn around the Professional Services Division of MGC in the mid 90’s, and for two years at least MGC PSD kept pace with Joe’s Spectrum Services; then six years after forming Henke Associates the writer had the privilege of actually working directly with Joe as Joe’s Acting VP of Marketing at think3  during that company’s most successful period; and of course the writer has followed Joe’s whereabouts ever since.

[4] At this point, the writer decided to hold the first Oasys interview in abeyance, until a particular subsequent event occurred.

[5] At this moment during the first interview, Nanette later confessed, she had begun to muse privately about The Netherlands, purported to be “the land of giants,” having noticed that Paul van Besouw and Harm Arts were both well over six feet tall.  (For more on this phenomenon, see The New Yorker article titled, The Height Gap, from April 2004 found at:

[6] This is the news we anticipated in [4]. Following this event was when the two interviews were combined.



About the Writer:

First of all, The writer is delighted to be able to bring such a compelling, real-life story to his readers.  A dedicated and articulate CEO surrounded by a great but lean team, tackling and ultimately succeeding in achieving a breakthrough solution to one of the biggest and complex challenges in EDA, yet still courageous enough to continue to carry the enterprise carefully and patiently though toward genuine commercial success, attracting and then listening to wise counsel from dedicated industry superstars. 

The writer is likewise grateful to the team who gathered this information, then worked with Paul Van Besouw and the writer to produce this article: Nanette Collins and Paul McCellan, with photo support from Oasys’ Bob Widman.

Since 1996, Dr. Russ Henke has been active full time as president of HENKE ASSOCIATES, a San Francisco Bay Area high-tech business & management consulting firm. The number of client companies served by HENKE ASSOCIATES during those years now numbers close to fifty. Engagement lengths have varied from a few weeks up to ten years and beyond.

During his previous corporate career, Henke operated sequentially on "both sides" of MCAE/MCAD and EDA, as a user and as a vendor. He's a veteran corporate executive from Cincinnati Milacron (Research Scientist), SDRC (President & COO), Schlumberger Applicon (Executive VP), Gould Electronics (President & General Manager), ATP (Chairman and CEO), and Mentor Graphics (VP & General Manager).

Henke is a Fellow of the Society of Manufacturing Engineers (SME) and served on the SME International Board of Directors. Henke was also a board member of SDRC, PDA, ATP, and the MacNeal Schwendler Corporation, and he currently serves on the board of Stottler Henke Associates, Inc.

Henke is also a member of the IEEE and a Life Fellow of ASME International.

In April 2006, Dr. Henke received the 2006 Lifetime Achievement Award from the CAD Society, presented by CAD Society president Jeff Rowe at COFES2006 in Scottsdale, AZ. In February 2007, Henke became affiliated with Cyon Research's select group of experts on business and technology issues as a Senior Analyst. This Cyon Research connection aids and supplements Henke's ongoing, independent consulting practice (HENKE ASSOCIATES).

Dr. Henke was also a contributing editor of the EDACafé.com EDA WEEKLY from November 01, 2009 until March 31, 2012, posting thirty-two EDA WEEKLY articles during that period; URL's available. Effective April 01, 2012 he contributes to EDA COMMENTARY and MCAD COMMENTARY, and also writes a periodic blog for and/or

Since May 2003 HENKE ASSOCIATES has also published more than 100 independent commentary articles on MCAD, PLM, EDA and Electronics IP on IBSystems' MCADCafé and EDACafé. Such Commentaries are now part of the EDA and/or MCAD COMMENTARY entries.

Further information on HENKE ASSOCIATES, and URL's for past Commentaries, WEEKLIES, etc., are available at

March 31, 2012 marked the 16th Anniversary of the founding of HENKE ASSOCIATES.