Although the industry is experiencing a shift from wire bonding to flip chip interconnect due to the increase in gold bonding wire costs, STATS ChipPAC has taken an aggressive approach to driving down the cost of flip chip technology. Until now, the high price of substrates and the elaborate and costly underfill step in flip chip technology have been barriers to flip chip adoption in mid- to low-pincount packages of 100 to 700 pins. For semiconductor companies interested in converting their package designs from a wire bond interconnect to flip chip interconnect, the typical industry cost premium has been in the 30% range.
STATS ChipPAC has achieved an unprecedented cost reduction with its low cost flip chip technology, essentially offering semiconductor companies the opportunity to have flip chip technology at price points below wire bond packaging. Rather than focusing on incremental changes in individual materials or processes, STATS ChipPAC took a comprehensive approach to reengineering the package structure and key processes to design the cost out of each element of flip chip technology, from substrate design to bump and the assembly process.
"The goal with our low cost flip chip program was to not merely identify ways to reduce the cost of our packages incrementally, but to have a clear breakthrough in fundamentally improving the cost of the flip chip packaging process," said Dr. Raj Pendse, Vice President, Technical Marketing, STATS ChipPAC. "Where a conversion to flip chip technology may have been cost prohibitive in the past, we are able to offer customers an advanced flip chip interconnect solution with a cost effective price point compared to wire bond packaging."
Since traditional substrate costs average 50% or more of the total package cost, STATS ChipPAC designed a new routing efficient interconnection scheme that reduces the substrate layer count and complexity. The company's new 2-layer laminate substrate design has a significantly lower cost than traditional 1-2-1 build-up substrates used for flip chip interconnection. The new substrate achieves equal or higher routing density with the same laminate substrate design rules as wire bond substrates.
The standard underfill process for flip chip interconnect is typically the slowest and single most expensive process step in the flip chip assembly process. In conjunction with the new interconnection and substrate design, STATS ChipPAC utilizes an efficient mold underfill technology which provides higher process throughput at a lower cost than conventional capillary underfill. Furthermore, in anticipation of the industry's shift to lead-free bump and halogen-free bill of materials, the low cost flip chip technology developed by STATS ChipPAC features a true lead-free bump composition which has proven to be effective with the mold underfill process.
Dr. Pendse continued, "We qualified the first phase of our low cost flip chip program in 2008 and today are in high volume production with packages such as Fine Pitch Ball Grid Array (FBGA) for mobile applications. As we move into the second phase of our program, through further innovation we are significantly increasing the routing density of our solution without stretching the substrate design rules. As a result, we believe we will be able to offer customers low cost flip technology for more than 75% of real die designs."
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, extent of deterioration in general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; customer credit risks; possible future application of push-down accounting; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; our ability to generate cash; potential impairment charges; availability of financing; adverse tax and other financial consequences if the South Korean taxing authorities do not agree with our interpretation of the applicable tax laws; classification of the Company as a passive foreign investment company; our ability to develop and protect our intellectual property; rescheduling or canceling of customer orders; changes in our product mix; our capacity utilization; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; shortages in supply of key components; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; changes in environmental laws and regulations; our ability to meet the applicable requirements for the termination of registration under the Exchange Act; our ability to meet specific conditions imposed for the continued listing or delisting of our ordinary shares on the Singapore Exchange Securities Trading Limited (SGX-ST); exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited ("Temasek") that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labor union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; and other risks described from time to time in the Company's filings with the U.S. Securities and Exchange Commission, including its annual report on Form 20-F dated March 9, 2009. You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.
About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.
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