Optimize in Less Time: Rapid Design Exploration with the Lynx Design System, July 19

 

How


Date: July 19, 2011
Time: 10:00 a.m. - 11:00 PST
Registration:  Click here to register!                                       

 

Overview

Every SoC design requires a unique implementation strategy to navigate the tradeoffs between power, performance and area to achieve the best results for the specific use. For instance, how do different tool switches influence clock frequency and what is the resulting impact on power?   How will different floorplans impact congestion?  How will different standard cell libraries and embedded memories impact power and area?  The keys to successful design exploration include getting to answers rapidly and in a systematic fashion with as much automation as possible.  With the Lynx Design System’s advanced graphical design exploration capabilities, you can run these and other experiments faster and with significantly less effort. 
 
Using three commonly used design strategies, we will demonstrate how the Lynx Design System’s design exploration capabilities can help you to create an optimal design for your SoC.  You will see how Lynx can help you quickly evaluate the impact of different process technologies and standard cell libraries on your design implementation.  We will show you how Lynx’s graphical flow environment can be used to perform rapid and accurate "what-if" analyses to tune both the design and the design flow. We will also demonstrate how to rapidly set up and automate multiple place and route runs in parallel to determine an optimal floorplan.
 
Who should attend:  Front end and backend design engineers, CAD engineers, flow developers and project leads.

Register Now!




Review Article Be the first to review this article
CST: Webinar

Aldec Simulator Evaluate Now

Featured Video
Jobs
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
DSP Tools Engineer for Cirrus Logic, Inc. at Austin, TX
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Design Verification Engineer for Cirrus Logic, Inc. at Austin, TX
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Upcoming Events
IC Open Innovation Panel During REUSE 2017 at Santa Clara Convention Center 5001 Great America Parkway Santa Clara CA - Dec 14, 2017
Essentials of Electronic Technology: A Crash Course at Columbia MD - Jan 16 - 18, 2018
Essentials of Digital Technology at MD - Feb 13 - 14, 2018
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise