Increasing demand for more advanced electronic products with superior functionality, higher I/O density and increased performance in a smaller form factor is driving technology integration at the die and package level. Fan-out wafer level technology offers the ability to provide a higher number of interconnects than is possible with fan-in wafer level technology. The cornerstone of STATS ChipPAC's fan-out wafer level technology platform is embedded Wafer-Level Ball Grid Array (eWLB). With over 100 million units shipped from its Singapore operation, STATS ChipPAC has established itself as the manufacturing and volume leader for this technology with capabilities in both 200mm and 300mm wafer formats.
"As die sizes and lithography nodes continue to shrink, the challenge is to find the most efficient way to integrate more functionality and performance into a final solution. In order to address these complex challenges, advanced packaging is playing an increasingly vital role in functional integration. By combining eWLB technology with our Through Silicon Via (TSV) and Integrated Passive Device (IPD) technology we are achieving new levels of heterogeneous integration in a wide range of design configurations including small die, large die, multi-die, multi-layer and stacked packages," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.
eWLB is a powerful wafer level technology that has the design flexibility to accommodate an unlimited number of interconnects and is unconstrained by die size. This has allowed eWLB to meet the relentless form factor requirements and performance demands of the mobile and handheld market. STATS ChipPAC's significant focus and investment in the evolution of this technology has resulted in an expanded range of package architectures. This includes single die, multi-die, ultra thin, System-in-Package (SiP) and three dimensional (3D) packaging, all with superior electrical and thermal operating characteristics. With its many technology attributes including a solid integration platform and a revolutionary structure which makes it inherently one of the thinnest package profiles in the industry, eWLB appeals to an increasingly broad range of market applications.
STATS ChipPAC offers a number of advanced package architectures which integrate eWLB with TSV and IPD. TSV technology enables the integration of semiconductor die fabricated in different technology nodes with diverse testing requirements. The short vertical TSV interconnections through the silicon wafer achieve greater space efficiencies for a smaller form factor and higher electrical performance. Passive devices such as resistors, capacitors, inductors, filters and baluns can consume 60% to 70% of available space in a system, subsystem or SiP package. Integrating TSV and IPD technology in an eWLB design delivers clear advantages such as advanced heterogeneous system integration, higher electrical performance and reduced form factor packaging.
Dr. Han continued, "The ability we have to integrate TSV and IPD with eWLB technology opens up a wide range of possible design configurations for SiP and 3D packaging at the silicon level. This is an effective approach to system partitioning which offers our customers an overall better system performance."
STATS ChipPAC will be presenting the latest information on eWLB, TSV, IPD and other innovative technologies such as fcCuBE and die-to-die copper wirebonding for 3D packaging at the Electronic Components and Technology Conference that is being held May 31st to June 3rd, 2011 in Orlando, Florida.
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, shortages in supply of key components and disruption in supply chain; general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited ("Temasek") that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited ("SGX-ST"). You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.
About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.
Investor Relations Contact: Tham Kah Locke Vice President of Corporate Finance Tel: (65) 6824 7788 Fax: (65) 6720 7826 email: Email Contact Media Contact: Lisa Lavin Deputy Director of Corporate Communications Tel: (208) 867-9859 email: Email Contact