SpyGlass® 4.5 Release Contains Many New Features – in Use by Customers Worldwide
San Jose, Calif., May 16, 2011 — Atrenta Inc., a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries, has announced the availability of the next-generation release of its popular SpyGlass® product family. SpyGlass 4.5 contains a number of innovations to further increase its impact across a broad range of advanced system on chip (SoC) designs and customer applications
Atrenta has enhanced the SpyGlass family in multiple areas, including usability, debug, advanced linting, power estimation and reduction, CDC verification, constraints management, and testability. SpyGlass is widely installed throughout the semiconductor and systems industries. There are over 170 customers comprising thousands of users at companies such as Renesas Mobile and STMicroelectronics. SpyGlass has become the de facto standard for advanced SoC designs.
The core SpyGlass infrastructure now offers an industry-standard Tcl command line interface that enables RTL designers to create specialized scripts for repetitive tasks, perform interactive query and exploration, debug interactively and generate/customize reports.
Debugging has been strengthened significantly through additional abstractions in the incremental schematic – allowing the user to focus on the specific logic related to a violation, thus reducing debug effort. The concept of ‘scenarios’ has also been introduced to allow more intuitive analysis and management of configurable and/or multi-mode designs.
Based on advanced formal analysis techniques, the SpyGlass CDC product now leverages ground-breaking structural analysis technology to accelerate the process of identifying and resolving clock domain crossing (CDC) problems. This new technology applies class-leading techniques to pin-point only the real CDC issues in a design and minimize the effort required to debug and fix them. The new hierarchal CDC analysis capability using an abstracted model for already analyzed blocks enables significant runtime improvements and virtually unlimited capacity to handle very large SoC designs.
The performance of the SpyGlass Constraints product has been further enhanced in this release to offer run times which are at par with typical static timing analysis (STA) tools for netlist designs, while continuing to offer fast constraint analysis at the RTL stage of the design flow. Users have reported performance improvements of up to 5X. Users will also see performance improvements when identifying clock to clock false paths - both the synchronous and asynchronous varieties.
The SpyGlass DFT and SpyGlass DFT DSM products have been enhanced to provide new capabilities for SoC DFT debug including the verification of IEEE 1149.1 and IEEE 1500 setup sequences through high-level Tcl commands. SpyGlass DFT DSM also supports the CPF & UPF power intent formats to verify power management circuitry under test mode conditions. The SpyGlass MBIST product now supports a Tcl-based flow for RTL memory built-in self test insertion.
The SpyGlass Power product family has been enhanced to support new strategies for low power verification with industry-leading support for both the CPF & UPF power intent formats. The performance of power verification has been substantially improved, in many cases by over 30% based on customer design runs. The RTL power estimation and reduction capabilities have been enhanced to support newer techniques to reduce more power around registers and memories. These techniques have shown 40% reduction in power on representative customer designs. Both sequential equivalence checking and formal technology are employed in the SpyGlass Power family.
And finally, the popular SpyGlass DashBoard and DataSheet reports have a simplified report structure for easy portability, as well as a new look and feel that improves readability. These reports have found significant application in management dashboards for design tracking, audits, and development of rigorous handoff documentation to improve the quality of delivered IP.
SpyGlass 4.5 is now in production and available for download.
Atrenta is a leading provider of SoC Realization solutions for the semiconductor and electronic systems industries. As one of the largest private electronic design automation companies, Atrenta provides a comprehensive SoC Realization solution that delivers higher quality semiconductor IP, predictable design coherence, automated chip assembly and improved implementation readiness. Its SpyGlass® and GenSys® products and GuideWare reference methodologies open the way for broader deployment of system on chip (SoC) devices in the marketplace, improving time to market, reducing implementation costs and lowering risk. With over 170 customers, including 18 of the top 20 semiconductor and consumer electronics companies, Atrenta enables the most complex SoC designs in the world. Atrenta, the SoC Realization Company. www.atrenta.com
Atrenta, the Atrenta logo, SpyGlass and GenSys are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.