Altera's Quartus II Software Version 11.0 Features the Production Release of Qsys System Integration Tool

Industry's First FPGA-Optimized Network-on-a-Chip (NoC) Interconnect Delivers up to 2X the Performance versus SOPC Builder

SAN JOSE, Calif., May 9, 2011 — (PRNewswire) — Altera Corporation (Nasdaq: ALTR) today announced the release of its Quartus® II software version 11.0, the industry's number one software in performance and productivity for CPLD, FPGA and HardCopy® ASIC designs. Version 11.0 features the production release of Altera's next-generation system integration tool, Qsys. The new Qsys tool features the industry's first FPGA-optimized network-on-a-chip (NoC)-based interconnect delivering up to 2X higher interconnect performance compared to SOPC Builder. Qsys improves system scalability for large FPGA designs and enables support for industry standard interfaces (Avalon and AMBA® AXI™ from ARM®, etc).

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Qsys uses a NoC-based interconnect to deliver higher performance systems compared to conventional bus and switch fabric architectures. To demonstrate the capabilities of the high-performance interconnect in version 11.0, Altera offers a PCIe® to DDR3 reference design built using Qsys. The reference design achieves throughput of over 1,400MB/s between a memory-mapped PCIe Gen2 x4 Endpoint and an external DDR3 memory. The design uses an automatically pipelined, NoC-based interconnect to packetize data for easier and faster transport. The reference design demonstrates how an Altera-provided PCIe IP core saves months of development time by eliminating the need to develop Transaction Layer Packet (TLP) encoding/decoding logic and by simplifying PCIe protocol interface complexity. Customers can download the reference design from the Qsys page of Altera's Web site at www.altera.com/qsys.

Qsys simplifies the development of large, scalable systems with a hierarchical design flow feature. Using hierarchy, designers can divide large FPGA designs that include a high number of IP cores or system components into smaller sub-systems. The hierarchical design flow in Qsys allows designers to easily manage each sub-system while giving them the ability to add additional sub-systems to the design with minimal impact on system performance.

Qsys delivers the highest flexibility by automatically handling the bridging between multiple interface standards. Designers leveraging Qsys can develop systems using Avalon-based, Qsys-compliant IP cores, and can add IP cores that use a different industry standard interface in the future without replacing the original IP cores. Qsys supports the open-standard Avalon interface with this release. Future releases of Qsys will support additional industry-standard interfaces, such as AMBA AXI from ARM.

"Customer adoption of the beta release of Qsys exceeded our expectations and we are pleased to offer the production release today," said Chris Balough, senior director of software, embedded, and digital signal processing (DSP) marketing at Altera. "Customers using Qsys will see firsthand the productivity benefits the tool provides, including higher system performance, improved system scalability and faster development with the memory mapped PCIe IP core."

Quartus II software version 11.0 provides faster board bring up through enhancements to the software's external memory interface toolkit and transceiver toolkit. New performance and monitoring capabilities in the external memory interface toolkit improves productivity by helping achieve maximum memory efficiency. The enhanced transceiver toolkit delivers an improved channel manager interface and an updated transceiver control panel, so designers can optimize their transceivers for improved signal integrity and bring their boards up faster.

Additional Features Within Quartus II Software version 11.0 Include:

  • New Device Support—Provides final timing models and FPGA programmer object file support for all Cyclone® IV GX FPGAs. Quartus II Software version 11.0 also offers support for expanded transceiver modes for Stratix® V FPGAs.
  • Enhanced Chip Planner—Provides improved usability when designing with Stratix V FPGA transceivers. These enhancements allow clock planning with support for PLL assignments across all channels.
  • Expanded OS Support for DSP Builder—Added support for 64-bit Windows and Linux operating systems.

For additional information about the features offered in Quartus II software version 11.0, visit www.altera.com/q2whatsnew.

Pricing and Availability

Both the Subscription Edition and the free Web Edition of Quartus II software version 11.0 are now available for download. Qsys is available in both the Quartus II Subscription Edition and Web Edition software. Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II software, the ModelSim-Altera Starter edition and a full license to the IP Base Suite, which includes 14 of Altera's most popular IP (DSP and memory) cores. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera's FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.

ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. ModelSim is a trademark of Mentor Graphics Corporation. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/legal.

Editor Contact:
Steve Gabriel
Altera Corporation
(408) 544-6846
Email Contact

SOURCE Altera Corporation

Contact:
Altera Corporation
Web: http://www.altera.com




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