ATopTech Place and Route Engine Included in TSMC’s EDA 28nm Routing Qualification Report

SAN JOSE, Calif. — (BUSINESS WIRE) — March 22, 2011 — ATopTech, Inc., the leader in next generation physical design solutions, has completed compliance test of the company’s Aprisa place and route engine for TSMC’s 28nm process technology. The latest version of Aprisa is now qualified and ready for designs in TSMC’s 28nm process. TSMC’s EDA qualification reports are available at TSMC-Online.

TSMC extensively tested Aprisa to ensure its compliance with 28nm process requirements, including design rules and design for manufacturing (DFM) practices. The results meet TSMC's accuracy and quality standards. Independent of TSMC’s tests, ATopTech has added additional functionality in Aprisa and Apogee, the company’s floor planning and chip assembly tool, in anticipation of 28nm design challenges.

“Having ATopTech’s place and route tool qualified for TSMC’s 28nm process technology is an important milestone,” said Suk Lee, director of design infrastructure marketing at TSMC. ”We are pleased with the progress of ATopTech supporting TSMC 28nm technology.”

“ATopTech's P&R technology is architected specifically for design in advanced technology,” said Jue-Hsien Chern, CEO of ATopTech. “Qualifying for TSMC’s 28nm process technology reiterates our commitment to always delivering cutting-edge solutions to our customers.”

About ATopTech

ATopTech, Inc., is the technology leader in IC physical design. ATopTech’s technology offers the fastest time to design closure focused on advanced technology nodes. The use of state-of-the-art multi-threading and distributed processing technologies speeds up the design process, resulting in unsurpassed project completion times. For more information, see www.atoptech.com.

Aprisa and Apogee are trademarks and ATopTech is a registered trademark of ATopTech, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

 

 



Contact:

Cayenne Communication LLC
Michelle Clancy, 252-940-0981
Email Contact

 




Review Article Be the first to review this article
Featured Video
Jobs
ASIC FPGA Verification Engineer for General Dynamics Mission Systems at Bloomington, MN
Principal Engineer FPGA Design for Intevac at Santa Clara, CA
SOC Logic Design Engineer for Global Foundaries at Santa Clara, CA
Development Engineer-WEB SKILLS +++ for EDA Careers at North Valley, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Technical Marketing Manager Valley for EDA Careers at San Jose, CA
Upcoming Events
DVCon 2017 Conference at DoubleTree Hotel San Jose CA - Feb 27 - 2, 2017
IoT Summit 2017 at Great America ballroom, Santa Clara Convention Center Santa Clara CA - Mar 16 - 17, 2017
SNUG Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Mar 22 - 23, 2017
CDNLive Silicon Valley 2017 at Santa Clara Convention Center Santa Clara CA - Apr 11 - 12, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy