As semiconductor devices are scaled to advanced wafer technology nodes of 45/40nm and below, innovations in package structure, design and assembly process are key to achieving high performance, cost-effective product solutions. fcCuBE technology addresses a complex set of packaging challenges and delivers important benefits including:
- Ultra high I/O escape routing density
- Scalability to very fine bump pitches of 80 micron and below with finer effective
- Significant reduction of stress on Ultra low-k (ELK/ULK) structures that has been proven down to 45/40 nanometer (nm) and 28nm silicon structures
- Broad fab node compatibility
- Higher resistance to electromigration
- Lead-free alternative to conventional lead-free bumps and solder-based bumps
- A 20-40% lower cost over standard flip chip packages for most designs
"We have taken our innovative Low Cost Flip Chip technology and enhanced it to achieve greater design flexibility and performance across a broader range of applications, I/O requirements and fab nodes. The compatibility of fcCuBE technology with advanced silicon nodes has been proven down to 45/40nm, and early testing at the 28nm silicon node have shown equally promising results. The significance of fcCuBE comes from the combination of advancements we have made in materials, structure and manufacturing process capabilities," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.
fcCuBE technology is based on STATS ChipPAC's patented BOL interconnect structure which has been combined with Cu column bump to deliver an ultra high I/O escape routing density with a finer bump pitch compared to standard solder bumps. The advancement enables more relaxed substrate design rules than standard flip chip packaging and provides scalability to very fine bump pitches of 80 micron and below.
The fcCuBE solution also offers a significant reduction of flip chip packaging stress on ELK/ULK structures in advanced silicon nodes and a higher resistance to the electromigration phenomenon which can result from the higher current density induced by the scaling of features. Although copper is a harder bump material that can cause damage to ELK/ULK layers in finer silicon nodes, the fcCuBE interconnect structure provides an effective solution to the challenges in the semiconductor industry. STATS ChipPAC has completed extensive thermo-mechanical simulation testing on fcCuBE technology with results demonstrating a significant reduction of stress on ELK/ULK structures which are consistent with empirical data generated with 45/40nm as well as 28nm node product test vehicles.
In terms of the design flexibility of fcCuBE, Dr. Han said, "We are seamlessly deploying the core fcCuBE technology beyond traditional single-die flip chip packaging into more complex stacked/3D packages including Package-on-Package (PoP), Package-in-Package (PiP), flip chip/wire bond hybrid packages and next-generation Through Silicon Via (TSV) configurations."
The robust fcCuBE interconnect structure has proven to be a successful lead-free alternative to solder-based bump structures and supports the semiconductor industry's transition to environmentally friendly materials in flip chip packages. fcCuBE technology has demonstrated excellent reliability, exceeding the industry minimum requirements using JEDEC standard tests.
"fcCuBE technology is raising the bar on what flip chip packages can deliver in terms of increased performance, superior reliability and miniaturisation with a compelling value at low price points. We have enhanced our technology to achieve an advanced flip chip solution that scales to finer silicon nodes and uses our standard, cost-effective manufacturing process to deliver fcCuBE at a price point that offers a clear competitive advantage for our customers. fcCuBE technology is a compelling solution for a wide cross section of end products in the mobile/handheld, computing and high-end network/telecom markets," said Dr. Raj Pendse, STATS ChipPAC's Vice President of Product and Technology Marketing.
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; shortages in supply of key components; customer credit risks; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited ("Temasek") that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited ("SGX-ST"); and other risks described from time to time in the Company's filings with the U.S. Securities and Exchange Commission, including its annual report on Form 20-F dated 5 March 2010. You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.
About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.
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