STARC Adopts ICScape RCExplorer Early Layout Parasitic Extraction and advanced Interconnect Analysis Solutions in the STARCAD-AMS Design Flow

San Jose, California, USA – ICScape, Inc., a technology leader in timing analysis and design closure solutions, today announced that STARC, the Japanese electronic design consortium co-founded by major Japanese semiconductor companies, has validated ICScape’s RCExplorer™ Early layout parasitic extraction and advanced interconnect analysis for advanced process technologies, and included them in its STARCAD-AMS Design Flow.

STARCAD-AMS Design Flow covers comprehensive requirements in mixed signal design methodology for 65nm and below process technologies, with the emphasis on improving turnaround time, inter-block co-design, concurrent schematic-layout design and product quality and usability. ICScape has closely worked with STARC on the requirements through RCExplorer enhancements. RCExplorer has demonstrated its unique capability for partial routed extraction to provide early design verification for critical area of design to enable concurrent schematic-Layout design environment.

"The goal of the STARCAD-AMS Design Flow is to develop the most efficient and comprehensive design methodology to reduce turnaround time by half for STARC member companies," said Kunihiko Tsuboi, Senior Manager at STARC. "ICScape effectively addresses our requirements in performance, accuracy, advanced analysis features, and product quality. We are pleased the adoption of RCExplorer in our STARCAD-AMS  Design Flow and provide our member companies a solution with the biggest productivity gains for very complicated designs in 65nm and below processes."

"We have closely worked with STARC on the Deign Flow that covers broad and stringent requirements in concurrent Schematic-Layout analysis for complicated designs using 65nm or below process technologies," said Steve Yang, president of ICScape. "We are pleased that ICScape was able to deliver the required solutions. STARC's adoption of RCExplorer into the Design Flow shows our continuing effort to our customers with the most leading timing analysis technologies."

About ICScape
ICScape, Inc. is a leading Electronic Design Automation (EDA) tools provider for multiple-mode-multiple-corner (MMMC) clock tree analysis and optimization, MMMC Timing ECO, leakage power reduction  for multi-million-gate nanometer designs and parasitic extraction and analysis for AMS designs. ICScape’s products are being used at leading semiconductor, fabless, and design services companies worldwide and have produced numerous successful tape-outs in different design application areas. ICScape has offices in San Jose, California and Wang Jing Hi-tech Park, Beijing China, and distributors in Japan, Taiwan, Korea, and Israel. For more information, please visit, email to Email Contact or call 408-263-3900

Semiconductor Technology Academic Research Center (STARC) is a research consortium co-founded by major Japanese semiconductor companies in December 1995. STARC's mission is to contribute the growth of the Japanese semiconductor industry by developing leading-edge SoC design technologies.
For more information please visit .

Press Contact:
Showming Chen, ICScape, Inc., 408-263-3900
Email Contact

RCExplorer is trademark of ICScape, Inc. All other trademarks and trade names are the property of their respective holders.

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