NextOp Software Selects Verific Design Automation SystemVerilog

ALAMEDA, CA -- (MARKET WIRE) -- Jan 20, 2011 -- Verific Design Automation today said that NextOp Software, Inc. has licensed its software for use with the NextOp assertion-based verification solutions that allow design and verification teams to uncover bugs, expose functional coverage holes, and increase verification observability.

NextOp Software tightly integrated Verific's SystemVerilog parser and static and register transfer level (RTL) elaborators with BugScope assertion synthesis, a tool that synthesizes high-quality assertions and functional coverage properties from the RTL design and testbench.

"Verific's SystemVerilog solution was referred to us by one of our key strategic accounts," notes Yunshan Zhu, NextOp Software's president and chief executive officer. "We have been impressed with Verific's SystemVerilog solution and its technical support team. Our assertion technology requires extensive language elaboration, all of which Verific fully supports."

Since its founding in 1999, Verific's parsers and elaborators have become the industry's de facto standard. In addition to NextOp Software, its software serves as the front end to a wide range of Electronic Design Automation (EDA) and Field Programmable Gate Array (FPGA) tools for analysis, simulation, verification, synthesis, emulation and test of RTL designs. Verific's software is distributed as C++ source code and compiles on all 32- and 64-bit Unix, Linux, and Windows operating systems.

Concludes Michiel Ligthart, Verific's chief operating officer: "NextOp Software is a great example of the creativity and ingenuity alive and well in EDA. It's been a pleasure to work with its development team."

About Verific Design Automation
Verific Design Automation, with offices in Alameda, Calif., and Kolkata, India, provides de facto standard front-end software supporting SystemVerilog, Verilog and VHDL design. Verific's software is used worldwide by the EDA and semiconductor community in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping, and design-for-test applications, which combined have shipped more than 40,000 copies. Corporate headquarters is located at: 1516 Oak Street, Suite 115, Alameda, Calif. 94501. Telephone: (510) 522-1555. Facsimile number: (510) 522-1553. Email: Email Contact. Website: www.verific.com.

NextOp Software and Verific Design Automation acknowledge trademarks or registered trademarks of other organizations for their respective products and services.

For more information, contact:
Nanette Collins
Public Relations for Verific
(617) 437-1822

Email Contact 





Review Article Be the first to review this article
Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Diversity: Really, who cares
More Editorial  
Jobs
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Proposal Support Coordinator for Keystone Aerial Surveys at Philadelphia, PA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
The Rise of Mechatronics at Dassault Systèmes San Diego 5005 Wateridge Vista Drive San Diego CA - Sep 12, 2017
The Rise of Mechatronics at Buca di Beppo - Pasadena 80 West Green Street Pasadena CA - Sep 13, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy