STATS ChipPAC’s Copper Wire Bond Production Exceeds 100 Million Units with Rapid Volume Ramp
Singapore – 11/30/2010, United States – 11/29/2010 – STATS ChipPAC Ltd. (“STATS ChipPAC” or the “Company” – SGX-ST: STATSChP), a leading semiconductor test and advanced packaging service provider, today announced it has shipped over 100 million semiconductor packages with copper wire bond interconnect and expects copper wire bond production volume to grow another 75% by the end of 2010 due to a rapidly growing customer base.
While copper has been used in the semiconductor industry as an interconnect material for many years, there has been a recent surge in demand due to the fact that copper represents one of the most significant savings in material costs available today. The high price of gold has driven a rapid shift to copper as an attractive alternative to achieve cost savings in semiconductor packages. Originally used for low leadcount power devices, copper wire use has now expanded into mid- and high-end Input/Output (I/O) packaging, both leadframe and laminate substrate based, and has been proven on advanced wafer fabrication nodes and fine pitch devices where it offers both a lower cost solution with improved performance. Copper wire provides better conductivity than gold or aluminum, improved electrical and thermal performance, and stronger mechanical properties.
“We are seeing a strong increase in demand for copper wire interconnect in mobile, consumer and computing applications as customers look for cost effective solutions,” said Wan Choong Hoe, Executive Vice President and Chief Operating Officer, STATS ChipPAC. “We have a robust manufacturing process inside a Class 1000 cleanroom environment that is consistently delivering yields comparable to gold wire bonding.”
With five manufacturing facilities in Asia that have copper wire bond capabilities, STATS ChipPAC offers customers a wide range of leaded and laminate packages with copper interconnect and has been actively implementing process capabilities for wafer nodes ranging from 250nm down to 45/40nm with Low-K and ELK dielectric materials. Development work is continuing at a rapid pace on more advanced wafer nodes, finer pad pitches, stacked die packaging and die-to-die bonding.
Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilization; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; shortages in supply of key components; customer credit risks; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited (“Temasek”) that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labor union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases, the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited (“SGX-ST”); and other risks described from time to time in the Company’s filings with the U.S. Securities and Exchange Commission, including its annual report on Form 20-F dated March 5, 2010. You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.
About STATS ChipPAC Ltd.
STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.
Investor Relations Contact:
Tham Kah Locke
Vice President of Corporate Finance
Tel: (65) 6824 7788, Fax: (65) 6720 7826
email: Email Contact
Deputy Director of Corporate Communications
Tel: (208) 867-9859
email: Email Contact