Evatronix to Discuss Digital and Mixed Signal IP Design Issues at the IP-SoC 2010 Conference in Grenoble

How to apply efficient verification to mixed signal IP? Will a SuperSpeed USB 3.0 digital IP run on an 8-bit microcontroller? Find the answers during Evatronix sessions.

Bielsko-Biala/Poland — November 15, 2010 — Evatronix SA has announced today the presentation of two technical papers at the annual IP –SoC Conference in Grenoble, France on Nov 30th - Dec 1st, 2010. The speeches will address the key issues in the SoC design domain – verification and application development. The 2010 IP-SoC Conference will be the 6th consecutive IP-SoC event to which Evatronix contributes with technical papers.

SESSION 1 - SYSTEMATIC APPROACH TO VERIFICATION OF A MIXED SIGNAL IP. HSIC PHY CASE STUDY

This paper discusses the verification process of a mixed signal core of an HSIC PHY. After explaining the specific topic related with HSIC comparison to USB, Evatronix will demonstrate the verification strategy. It will be explained from the top level point of view, together with detailed description covered in subsequent sections. Then the system level testbench and interoperability testbenches will be explained parallel to local testbenches for analog block characterization. Finally, the testchip verification procedure will be presented. The methodology is based on robust analog and digital design flows, where the usage of mixed signal simulators allows combining these flows and increases level of the verification.

SESSION 2 – USB 3.0 APPLICATION BUILDING USING LOW PERFORMANCE 8-BIT MICROCONTROLLER

During this session Michal Jedrak, Technical Marketing Manager at Evatronix, will present the aspects of building a SuperSpeed USB 3.0 application using a low performance 8-bit microcontroller, taking an 8051 derivative as an example. After a technical overview of the USB technology and its performance, the example architectures will be discussed and followed by description of target applications based thereon. Besides the architectural view also the software side and its performance will be discussed. To give the full view the silicon area demands and power consumption will also be presented.




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