Lynguent Part II

So AMS models are the backbone of an AMS design flow. They are required during the design phase, but also they are necessary for verification where behavioral models of portions of the chip matched to the behavior observed in a transistor level simulation may be used. To allow for continual refinement of a model during design, and to provide improved performance compared to a transistor level simulation during verification such models are written using an HDL: Verilog-A, Verilog-AMS, or VHDL-AMS.

Enter Lynguent’s Approach: Graphical Creation of Models

The Lynguent approach is based on the observation that designers typically prefer not to write code, but they are familiar with schematic capture systems. A schematic capture system supports the composition of a design by placing model instances on a canvas and connecting their ports. Lynguent’s ModLyng™ Integrated Modeling Environment (IME) provides an equivalent functionality to compose an individual model. With the ModLyng IMETM, a designer places building blocks from a library on the canvas and then connects their ports to describe the functionality of the model.

Consider the diagram below – which of the four approaches shown is most appealing?

Building blocks are very similar to models, i.e. they have ports, parameters and an implementation, and they are created and maintained in the ModLyng IME just like models. They typically implement a simple transformation of their inputs, which by itself may not seem very interesting, but their power becomes apparent when combined with other building blocks. Because of their simplicity building blocks become reusable immediately, and they enable the graphical composition of a model. Building blocks often cannot be simulated in isolation, but models constructed from building blocks are ready to be simulated: when the model is exported to be used by a simulator, the ModLyng IME arranges the code associated with the building blocks such that a correct model is generated.

Each of the Lynguent products includes several libraries of building blocks. Examples of such building blocks are comparators with or without hysteresis, mathematical functions, logic operations, various kinds of stimulus, and many more. Some building blocks even provide some event-driven capabilities for Verilog-A; traditionally Verilog-AMS would have been required for this functionality. Models constructed from the building blocks can be simulated with a variety of simulators supporting Verilog-A, Verilog-AMS, VHDL-AMS, and MAST®. (B, C, D).

The figure above demonstrates these capabilities. The pane on the right shows the implementation of an oscillator combined with a resettable counter. The frequency of the oscillator is selectable with the inputs A1 through A4. Their values are converted to a decimal number that is used to look up the frequency value in a table. This value then drives the actual pulse generator, whose output connects to the pulse counter and also to a value splitter. Their values are converted from a simple variable, indicated by purple wires, to electrical, indicated by black wires. The top left of the pane implements the reset logic. The left pane shows a collection of building block libraries loaded into the ModLyng IME, with the eb_Inverter_VV model selected. An instance of the model is annotated in the right pane.

Composing a model using building blocks has several important advantages over creating it using the HDL:

  • The building blocks and their interconnection (the topology) reflect the function of the part and provide an intuitive documentation for its internal organization.
  • The model creator does not have to worry about language syntax and semantics, as she works with graphical symbols to create a model of a part.
  • The number of engineers able to create a behavioral model of a part increases significantly because no language skills are required for this task.
  • Graphical composition of models is intuitive even if not done frequently.
  • A model can be exported to several different dialects of a language and even to different languages from the same topology. To this end, the ModLyng IME will apply suitable transformations where necessary.
  • Lynguent, Inc. provides several libraries of building blocks, but users can create their own. To create a new building block minimal language skills are required.
  • Building blocks are typically relatively simple. As a consequence:
  • Building blocks can be reused in many different models.
  • It is easy for building block authors to understand the function of a building block.
  • Testing of building blocks is straightforward and quick.
  • Reuse of building blocks significantly reduces the risk of creating a new model because each building block is amply tested and known to work.

Models created from building blocks can themselves be placed in libraries. Lynguent, Inc. is using this approach to create libraries of AMS parts such as operational amplifiers, A/D converters, PLL’s, voltage regulators, and others. Each such model may have several versions that reflect different implementations of the part. For example, different model versions exist for A/D converters with binary or Grey encoding and flash, successive approximation and Wilkinson structures. Each also has a corresponding testbench, which in the Lynguent environment is just another model. The fact that these libraries of parts and testbenches are built from building block libraries immediately allows the parts to be exported to any of the supported languages and dialects.

Creation of Verification Models from Netlists

Creating a behavioral model of a semiconductor part intended to match the behavior of some transistor level simulation, typically based on a Spice netlist, builds on the foundation provided by the ModLyng IME and the building block libraries, but requires additional considerations. The process requires a basic understanding of what the part does and how it is organized, i.e. what functional blocks were used to create the part. This understanding may be gained from design documentation or from behavioral models used during the design phase.

A behavioral model created in a ModLyng DV Studio using the building block approach provides this information naturally.

As a first step a testbench is created that allows the transistor level model to be simulated in a context that reflects its use. The testbench will typically be obtained from a testbench library provided by Lynguent, Inc. and adapted to the specific needs of the device. Testbench creation includes defining the simulation scenarios to capture: stimulus, simulation parameters, and performance measures to capture, e.g. a rise time, an overshoot, or a waveform over time. The testbench with the netlist representing the transistor level model as device under test is then simulated from the ModLyng DV Studio to generate the target results to which the behavioral model will be matched.

The second step of the process is the creation of a behavioral model of the device with parameters that can be adjusted in a later step to match the target results. The behavioral model will typically be created using a model from the Lynguent parts library as a starting point, augmented as necessary with building blocks from the libraries available in the ModLyng DV Studio. Understanding the function and structure of the device is essential for this step.

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