GRID Simulation Technology Announces NanoRAIL-TR for EMIR Simulation and Sign-off for Mixed-signal, Memory, Analog, and I/O Circuit Designs

Hierarchical SPICE-accurate Technology Delivers Breakthrough in Speed, Accuracy and Capacity

San Jose, CA and Tokyo, Japan - August 18th, 2010   

GRID Simulation Technology, Inc. (GST), a Silicon Valley-based Electronic Design Automation (EDA) company announced NanoRAIL-TR, the industry’s first hierarchical, parallel, distributed architecture (HPDA™) Electromigration and IR drop (EMIR) simulator for SPICE-accurate, giga-scale, transistor-level analysis, and sign-off of mixed-signal, memory, analog and I/O circuit designs.  NanoRAIL-TR’s unique HPDA architecture takes advantage of both standalone and networked multi-core systems delivering breakthrough in speed, accuracy, and capacity. HPDA scales linearly on standalone and networked multi-core systems.

Today’s low power IC designs implemented in advanced processes, require SPICE-accurate EMIR analysis to simulate, model, and verify large complex power delivery networks to ensure low power circuit performance, manufacturability, and product reliability. To handle these complex power networks, EMIR simulators employ hidden reduction methods to simplify the size of the networks being analyzed. While these methods reduce runtimes, they may cause a critical loss of accuracy in simulation and the loss of traceability between simulation results and the original circuit under evaluation.

NanoRAIL-TR’s  “Loss-less Partitioning™” Delivers SPICE-accurate EMIR Analysis

NanoRAIL-TR’s Loss-less Partitioning™ technology delivers SPICE accuracy and does not use reduction methods in network, model, or matrix calculations. It strictly adheres to Kirchhoff’s Voltage Law (KVL), Kirchhoff’s Current Law (KCL), and Power conservation law for all nodes without exception, providing fundamentally consistent EMIR simulation results. 100% node reporting, and 1-to-1 traceability between EMIR analysis and the physical design netlist are unique features of NanoRAIL-TR. To ensure easy integration into design flows, NanoRAIL-TR works with industry proven layout extractors and SPICE simulators.

Market Response

"High capacity, SPICE accurate analysis, modeling, and reporting functions are required for efficient EMIR simulation, verification, and sign-off,” said Mitsuo Saito, Chief Fellow and VP of Engineering, Toshiba Semiconductor. "Standard integration with trusted layout extraction and SPICE simulation tools using proven data formats reduces risks and improves benefits. This approach provides access to NanoRAIL-TR’s EMIR analysis, modeling and reporting capabilities without having to re-qualify proven extractor and circuit simulator functions. We look forward to continuing success working with GRID Simulation Technology in Toshiba Semiconductor’s advanced process low power design methodologies.

“We are excited to be working Toshiba Semiconductor with NanoRAIL-TR and SimCHECK to addresses their critical low-power needs for advanced process designs,” said Wai Yan Ho, CEO of GST.  “NanoRAIL-TR provides SPICE-accurate results. GST’s HPDA simulation methodology delivers to Toshiba design teams a hierarchical modeling architecture that improves EMIR analysis quality of results (QoR), quickly calculates total power consumption, and improves design performance and reliability.  We will continue to introduce new innovative technologies to meet the challenges facing IC designers.”

About GRID Simulation Technology

GRID Simulation Technology, Inc. is a Silicon Valley-based Electronic Design Automation (EDA) company dedicated to solving the world's largest and most complex electronics problems at true SPICE-accuracy through its revolutionary new analysis technology. The company's flagship products, NanoRAIL and SimCHECK, provide analysis of IC power grid problems including IR voltage drop and electro-migration (EM), and the qualification of complex power network analysis results. The company is a privately held California Corporation headquartered in Morgan Hill, CA with offices located in: Irvine, CA; East Fishkill, NY; and Tokyo, Japan.

For More Information

Contact:  John L Kulusich                                         

GRID Simulation Technology, Inc.
1295 East Dunne Avenue, Suite 215 Morgan Hill, CA 95037                                                             

NanoRAIL™ TR, SimCHECK™, HPDA™. and Loss-less Partitioning™ are trademarks of GRID Simulation Technology, Inc.

Review Article Be the first to review this article

ClioSoft at DAC

Featured Video
Senior Electrical Engineer for Allen & Shariff Corporation at Pittsburgh, Pennsylvania
Upcoming Events
DAC 2018 at Moscone Center West San Francisco CA - Jun 24 - 28, 2018
Symposium on Counterfeit Parts and Materials 2018 at College Park Marriott Hotel & Conference Center MD - Jun 26 - 28, 2018
Concar Expo 2018 at Convention Hall II Sonnenallee 225 Berlin Germany - Jun 27 - 28, 2018
Nanotech 2019 at Tokyo Big Sight East Halls 4-6 & Conference Tower Tokyo Japan - Jun 30 - 1, 2018
ClioSoft at DAC
TrueCircuits: IoTPLL

Internet Business Systems © 2018 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise