Research and Markets: Embedded Wafer-Level-Packages: Fan-out WLP / Chip Embedding in Substrate - The Next Generation of IC Packaging & Substrate Assembly Waves


  • Integrated semiconductor Device Manufacturers and fabless semiconductor companies
  • - Benchmark the industrialization status of embedded packaging technologies within the industry
  • - Identify possible partnership /or second source packaging subcontractors for your forthcoming developments
  • Assembly and Test Service companies
  • - Get the list of the main companies interested in Embedded WLP
  • - Screen possible new applications and technologies to support diversification strategy with embedded packaging platform
  • Equipment and Material suppliers
  • - Understand the differentiated value of your products and technologies in this emerging but fast growing market
  • - Identify new business opportunities and prospects
  • Electronic module makers and Original Equipment Makers
  • - Evaluate the availability and benefits of using embedded package components in your end system
  • - Monitor different embedded WLP suppliers to adjust your sourcing strategy
  • PCB and IC substrate manufacturers
  • - Monitor the evolution of IC packaging, assembly and test, especially linked to the emerging chip embedding PCB-based technologies, FO-WLP, IPD and 3D interposers

Key Topics Covered:

Scope of the Report & Definitions Executive Summary 1 - Embedded die Packaging of active ICs and passive components

  • Motivations and Drivers
  • Applications & End-markets:
  • Status of commercialization
  • - Cell-phone & Consumer applications
  • - Automotive applications
  • - Medical applications
  • 2009-2015 market forecasts for Embedded die packages
  • - In Package shipments (Munits)
  • - In Packaging revenues ($M)
  • Supply chain emerging for embedded die packages
  • - Players and positioning in the electronic value chain
  • - Who is the most aggressive in the commercialization?
  • - Who is doing what: partnership identified
  • Technology flavors for embedded package
  • - Chip first versus chip last?
  • - Single die embedding versus SiP module?
  • - Challenges related to yield & supply chain
  • Equt & Material Tool-Box for Embedded die
  • Cost structure for Embedded packages manufacturing
  • - Comparison with competitive package alternative that Embedded die technology is looking for direct replacement (QFN, BGA, WLCSP, SOT, PoP)
  • - Cost structure target of Embedded die for different application case (RFID, IPD, Power MOSFET / IGBT, DC/DC converters, PMU, Wireless Connectivity ICs, Digital Baseband, Memories, etc )
  • Conclusion on sweets spots for the introduction of Embedded die technology in the short / medium / long term
  • - Global Roadmap for Embedded die

2 - Fan-Out WLP package technology development

  • Motivations and market drivers
  • - Thermal performance of FOWLP package compared to FC-BGA package solution
  • Applications & status of commercialization
  • 2009-2015 market forecasts for FOWLP type of packages
  • - In Package shipments (Munits)
  • - In Packaging revenues ($M)
  • Supply chain emerging for FOWLP
  • - Players and positioning in the electronic value chain
  • - Who is the most aggressive in the commercialization?
  • - Who is doing what: partnership identified
  • FOWLP technologies & challenges
  • - Who owns the IP in this space?
  • - 1st generation versus 2nd generation FOWLP TMV Through Mold Via fabrication
  • - Panel size manufacturing for future FO-WLP
  • - Passive integration with FO-WLP technologies
  • Equipment & Materials for FO-WLP
  • - Challenges in new materials selection and missing equipments
  • Cost structure for FO-WLP manufacturing
  • - Competitive package alternative that FOWLP technology is looking for direct replacement (FC-CSP, FC-BGA, PoP, etc)
  • - Cost structure for FOWLP by application (RFEM module, PoP digital module, PMU chip, wireless baseband SOC chip, etc)
  • Conclusion on sweets spots for introduction of FOWLP technology in short / medium long term
  • - Global Roadmap for Fan-Out WLP

Review Article Be the first to review this article


Featured Video
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Reverie: All That Glitters is not Past
More Editorial  
SoC Design Engineer for Intel at Santa Clara, CA
Digital and FPGA Hardware Designer for Giga-tronics Incorporated at San Ramon, CA
Senior Physical Design Engineer for Ambiq Micro at Austin, TX
Technical Support Engineer for EDA Careers at Freemont, CA
Technical Marketing Manager Valley for EDA Careers at San Jose, CA
Upcoming Events
European 3D Summit 2017 at 3, parvis Louis Néel 38054 Grenoble France - Jan 23 - 25, 2017
3D Printing Electronics Conference at High Tech Campus 1, 5656 Eindhoven Eindhoven Netherlands - Jan 24, 2017
DesignCon 2017 at Santa Clara Convention Center Santa Clara CA - Jan 31 - 2, 2017
Embedded Neural Network Summit at San Jose CA - Feb 1, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy