GiDEL Announces The Availability Of TotalHistory™

A New Level in ASIC Prototyping and FPGA Debug

June 14, 2010, Anaheim, CA – GiDEL Inc., the first company to provide ASIC Prototyping Systems announced today the availability of TotalHistory™, the most advanced debugging feature available in today’s ASIC Prototyping solutions and FPGA based systems.

TotalHistory is a software only solution enabling users to define a list of signals in the design which they want to trace at full system speed. There is practically no limit on the number of signals traced. The user can then view the trace using a waveform viewer to debug and validate the design. Optionally, an API is available for queries by advanced users.

“TotalHistory enables users to have visibility of any signal in their designs, for virtually unlimited trace depth, with no or minimal degradation in performance”, said Reuven Wientraub, GiDEL’s Founder and CTO. “TotalHistory opens the horizon for new debug and validation methodologies including dumping internal data while running at customer site, finding random glitches in long runs, etc. It leverages the unique architecture of our systems eliminating the need of additional costly hardware.”

TotalHistory is available with GiDEL’s PROC_SoC ASIC Prototyping Systems and PROC Boards FPGA-based High Performance Computing (HPC) accelerators.

GiDEL is demonstrating TotalHistory at this year’s Design Automation Conference in Anaheim, California on June 14-16, at booth 912.

For more information on GiDEL’s PROC_SoC ASIC Prototyping Systems please see www.gidel.com/asic-prototyping.

About GiDEL

GiDEL is the first company to introduce ASIC Prototyping Systems and FPGA-based Vision, imaging and HPC acceleration solutions. It consistently leads the market with cutting-edge architectures, solutions and methodologies.

For more information please see www.gidel.com



Press Contact:
Coby Hanoch
+972-545-421-321
Email Contact




Review Article Be the first to review this article
CST: Webinar November 9, 2017

Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Teklatech: Work smart, Not hard
More Editorial  
Jobs
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Upcoming Events
ARM TechCon 2017 at Santa Clara Convention Center Santa Clara CA - Oct 24 - 26, 2017
MIPI DevCon Bangalore 2017 at The Leela Palace Bengaluru India - Oct 27, 2017
The 2017 International Test Conference at Fort Worth Convention Center Fort Worth TX - Oct 31 - 2, 2017
MIPI DevCon Hsinchu City 2017 at Sheraton Hsinchu Hotel Taiwan - Oct 31, 2017
CST: Webinar series



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise