Semiconductor Research Corporation and Cornell University Capture First-Ever Images of Sub-Nanometer Pore Structures in Low-K Materials

Research Provides a Solution to Reliably Visualize and Identify Low-K Issues That Greatly Affect the Speed and Power of Integrated Circuits

RESEARCH TRIANGLE PARK, N.C. — (BUSINESS WIRE) — June 8, 2010 — Semiconductor Research Corporation (SRC), the world's leading university-research consortium for semiconductors and related technologies, and researchers from Cornell University today announced a reliable method for visualizing and identifying the detailed structure of low-k insulating materials at a sub-nanometer scale. The ability to capture direct, quantitative images of pore structures – some smaller than one nanometer – helps solve semiconductor scaling concerns that could affect the future performance and power usage of integrated circuits.

To help maintain the ever-increasing power and performance benefits of semiconductors, the industry introduced very porous, low-dielectric constant materials to replace silicon dioxide as the insulator between nano-scaled copper wires. This sped up the electrical signals sent along these copper wires inside a computer chip, and at the same time reduced the power consumption. However, the detailed structure and connectivity of these nanopores have profound control on the mechanical strength, chemical stability and reliability of these dielectrics. With today’s announcement, researches now have a nearly atomic understanding of the three-dimensional pore structures of low-k materials required to solve these problems.

“Knowing how many of the molecule-sized voids in the carefully-engineered Swiss cheese survive in an actual device will greatly affect future designs of integrated circuits,” said David Muller, Professor of Applied and Engineering Physics and co-director of Kavli Institute for Nanoscale Science at Cornell University. “The techniques we developed look deeply, as well as in and around the structures, to give a much clearer picture so complex processing and integration issues can be addressed.”

So far, precise measurements using gas adsorption, X-ray reflectivity, small angle X-ray diffraction, neutron scattering and positron annihilation have been used. However, these methods lack the spatial resolution to explore process variations around individual devices where damage could occur. These methods also cannot give direct information about the individual 3-D pore shapes, connectivity and variations when integrated into a real device.

However, SRC and Cornell were able to devise its own method that they hope others will now begin to implement. Together, they were able to obtain 3-D images of the sub-1nm pores inside a low-k material using electron tomography with an annular dark-field scanning transmission electron microscope, providing quantitative, spatially-resolved information that can now be applied to low-k liner interfaces in integrated circuits to improve their performance and reliability.

“The electron tomography technique is a powerful 3-D extension of the widely employed 2-D STEM technique, but leverages the related 3-D imaging advances used for CT scans and MRIs in the medical field,” said Dr. Scott List, director of Interconnect and Packaging Sciences at SRC. “Sophisticated software extracts 3-D images from a series of 2-D images taken at multiple angles. A 2-D picture is worth a thousand words, but a 3-D image at near atomic resolution gives the semiconductor industry new insights into scaling low-k materials for several additional technology nodes.”

More details about the research can be found in the June 2 issue of Applied Physics Letters, which lists co-authors Huolin Xin, Peter Ercius, Kevin Hughes and James Engstrom along with Muller.

About SRC

Celebrating 28 years of collaborative research for the semiconductor industry, SRC defines industry needs, invests in and manages the research that gives its members a competitive advantage in the dynamic global marketplace. Awarded the National Medal of Technology, America’s highest recognition for contributions to technology, SRC expands the industry knowledge base and attracts premier students to help innovate and transfer semiconductor technology to the commercial industry. For more information, visit www.src.org.



Contact:

The Francisco Group
Dan Francisco, 916-293-9030
Email Contact




Review Article Be the first to review this article
CST: Webinar September 14, 2017

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Real Intent: Leveraging on Investments
More Editorial  
Jobs
FPGA Engineer for Teradyne Inc at San Jose, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise