Innovative Silicon Memory Presentation Selected for 2010 International Symposium on VLSI Technology, Systems and Applications

Dr. Wolfgang Mueller Delivering “DRAM and Embedded Memory” Presentation

SANTA CLARA, Calif. — (BUSINESS WIRE) — April 15, 2010Innovative Silicon, Inc. (ISi), developer of the Z-RAM® zero-capacitor, floating body (FB) memory technology, today announced that Dr. Wolfgang Mueller, the company’s director of device engineering and process integration, will be speaking at the 2010 International Symposium on VLSI Technology, Systems and Applications. Dr. Mueller’s Presentation “DRAM and Embedded Memory” will be presented as follows:

Venue:   VLSI Technology, Systems and Applications
Location: Ballroom A in the Ambassador Hotel in Hsinchu, Taiwan
When: Wednesday, April 28
Time: 3:20 p.m.
To attend:

Register at http://www.vlsi.itri.org.tw/reg/default.aspx

 

About the Topic:

DRAM technologies have been available in mass production at process geometries as low as 40-50nm for some time and key technology advances for the 30nm DRAM node have been published. As of today, there are no insurmountable technical roadblocks to scale one transistor, one capacitor (1T/1C) DRAMs to the 30nm node. However, capacitor dielectrics with capacitance equivalent (oxide) thickness (CET) of <0.5nm still need to be proven and the process complexity or cost to produce DRAMs at these dimensions increases drastically. Moreover, vertical cell structures need additional development in order to further reduce cell sizes to Four F Square (4F2). No known solutions exist to scale 1T/1C DRAMs below 30nm and the whole industry is investigating a replacement technology that can extend further dynamic memory to the 2x and 1x nodes.

This short course will cover stand-alone DRAM and embedded DRAM applications and will include a review of the potential roadmap challenges for 20nm technologies. The focus will be on the enabling unit processes, the cell structure, the capacitor structure, the capacitor materials, and the cell transistor. The required innovations for the periphery logic transistor scaling will also be discussed. The status and prospects for DRAM 1T/1C successor technologies such as floating body memory, PCRAM, and STT MRAM will also be reviewed.

About the Speaker

Dr. Wolfgang Mueller, a renowned memory expert, has been a key contributor to ISi’s Z-RAM technology development over the past year. Prior to joining ISi, Dr. Mueller served as Qimonda Fellow of DRAM Technology at Qimonda AG where he spearheaded a number of memory innovations including the development and implementation of “buried wordline” DRAM technology. During his tenure at Qimonda, Dr. Mueller also led the development team that transitioned Qimonda from trench capacitors to stacked capacitors and led the concept team working on the 4F2 DRAM bit cell. Dr. Mueller has presented at numerous industry conferences and has authored more than 50 papers and 20 patents. Dr. Mueller received his Ph.D. in electrical engineering from Vienna University of Technology in Vienna, Austria.

About Innovative Silicon

Innovative Silicon, Inc. (ISi) licenses its ultra-dense Z-RAM® floating body memory technology to stand-alone DRAM manufacturers so they may manufacture the lowest-cost, most-advanced memory ICs. Licensees include Hynix Semiconductor for use in advanced DRAM chips. The heart of the Z-RAM floating body technology is the “zero-capacitor,” single-transistor bit cell that eliminates the complex capacitor found in today’s DRAM technologies – making it the world’s lowest-cost and most-scalable memory technology. The company has closed in excess of $50 million in venture capital funding, received numerous industry awards, has been granted over 50 patents, and established R&D, engineering and support centers in Europe, Asia and North America. For more information see www.z-ram.com .

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