2010 Southwest DFT Conference May 5 to 6 - Registration Open

ON-LINE REGISTRATION OPEN

(Free registration closes May 1st)
CLICK HERE to REGISTER ( www.siliconaid.com/SWDFT_index.html)

SEE Detailed Agendas for both days below……

====================================================

Tutorial – May 5th

    Teachers - Alfred Crouch (ASSET), Teresa McLaurin (ARM), Stephen Sunter ( Mentor )

    9:30 - 10:00 On site Registration (coffee provided)

  • Introductions and Agenda

  • Trends and Principles of Mixed-Signal DFT and Test (S.Sunter)
    -Trends in process technology and design, such as digital vs. analog functional density, etc..
    -Trends in DFT and BIST of PLL, ADC/DAC, SerDes, RF, and miscellaneous analog (filters, buffers, regulators, etc.)
    -The 7 essential principles of practical analog BIST

  • LUNCH - Free lunch sponsored by SiliconAid

  • Multi-Core DFT Techniques (T.McLaurin)
    -Detailed Description coming

  • 3D Die Stack DFM (A.Crouch)
    -Detailed Description coming....

  • 4pm- Class ends


Conference Day – May 6th

8:00 - 8:30 On site Registration (coffee provided)
8:30 - 8:40 Welcomes and introductions
8:40 - 9:10 Key Note Address – Michael Lydon (Cisco Systems VP - Global Engineering and Operations)


Session 1
9:10 - 9:50 - Presentation 1 - Steve Comen ( Texas Instruments)
                     Title – Adaptive Test Efforts
9:50 - 10:30 - Presentation 2 - Jennifer Dworak - ( Brown Univ. )
                     Title – Online monitors correlate to functional tests
10:30 - 11:10 B R E A K
11:10 – 12:10 – Sponsor Presentations - (20 min each)
                      Title –Mentor Graphics, Asset InterTech
12:10 - 1:30 LUNCH - Free lunch


Session 2

1:30 – 2:10 - Presentation 4 – Mahmut Yilmaz (AMD)
                     Title – Scan DFT Features for latest uP Core
2:10– 2:50 - Presentation 5 - Carol Pyron (Freescale)
                    Title – IEEE 1149.6 and new dot 1 changes
2:50 - 3:30 - Presentation 6 - (Cisco)
                    Title – DFT Techniques at Cisco
3:30 - 4:10 B R E A K


Session 3


4:10 – 4:50 - Presentation 7 - Debo Sekoni (AltaSen)
                     Title – Talus Design with Scan Compression
4:50 – 5:30 - Presentation 8 – VC
                     Title – Industry Outlook
5:30 - 6:30 - Panel Discussion               Referee: Jim Johnson
5:30 - 6:30 Happy Hour during Panel


SPECIAL THANKS to our sponsors Mentor Graphics and ASSET InterTech.

Questions or companies interested in becoming a sponsor- Email Contact

 

ON-LINE REGISTRATION OPEN

(Free registration closes May 1st)

 

CLICK HERE to REGISTER ( www.siliconaid.com/SWDFT_index.html)

 

SEE Detailed Agendas for both days below……

====================================================

Tutorial – May 5th  

Teachers - Alfred Crouch (ASSET), Teresa McLaurin (ARM), Stephen Sunter ( Mentor )

9:30 - 10:00 On site Registration (coffee provided)

·         Introductions and Agenda

·         Trends and Principles of Mixed-Signal DFT and Test (S.Sunter)
-Trends in process technology and design, such as digital vs. analog functional density, etc..
-Trends in DFT and BIST of PLL, ADC/DAC, SerDes, RF, and miscellaneous analog (filters, buffers, regulators, etc.)
-The 7 essential principles of practical analog BIST

·         LUNCH - Free lunch sponsored by SiliconAid

·         Multi-Core DFT Techniques (T.McLaurin)
-Detailed Description coming

·          3D Die Stack DFM (A.Crouch)
-Detailed Description coming....

·          4pm -  Class ends

 

Conference Day – May 6 th  

8:00 - 8:30 On site Registration (coffee provided)
8:30 - 8:40 Welcomes and introductions
8:40 - 9:10 Key Note Address Michael Lydon ( Cisco Systems VP - Global Engineering and Operations)  

Session 1 
9:10 - 9:50 - Presentation 1  - Steve Comen ( Texas Instruments )
                 
Title – Adaptive Test Efforts
9:50 - 10:30 - Presentation 2 - Jennifer Dworak - ( Brown Univ. )
                 
Title – Online monitors correlate to functional tests
10:30 - 11:10  B R E A K
11:10 – 12:10 – Sponsor Presentations  - (20 min each)
                  
Title – Mentor Graphics , Asset InterTech
12:10 - 1:30 LUNCH - Free lunch
Session 2  
1:30 – 2:10 - Presentation 4 – Mahmut Yilmaz (AMD)   
                 
Title –  Scan DFT Features for latest uP Core
2:10– 2:50 - Presentation 5  - Carol Pyron (Freescale)
                  
Title – IEEE 1149.6 and new dot 1 changes
2:50 - 3:30 - Presentation 6  - (Cisco)  
                 
Title – DFT Techniques at Cisco  

3:30 - 4:10   B R E A K  

Session 3         

4:10 – 4:50 - Presentation 7  - Debo Sekoni (AltaSen)
                  
Title – Talus Design with Scan Compression
4:50 – 5:30 - Presentation 8 – VC  
                 
Title – Industry Outlook
5:30 - 6:30 - Panel Discussion              Referee: Jim Johnson
5:30  - 6:30 Hap py Hour during Panel

SPECIAL THANKS to our sponsors Mentor Graphics and ASSET InterTech.

Questions or companies interested in becoming a sponsor-   jim.johnson@siliconaid.com


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