Increasing The Level Of Abstraction Of IC Design

The recent introduction by Synopsys of Design Compiler 2010 has validated Oasys's Real Time Designer approach to IC design. When a startup company introduces a new approach to an old problem, the market always wonders whether or not the new solution will have traction among the design community. The absence of competition is a mixed blessing to startups. One the one hand, it makes it easier to sell the product to those who immediately appreciate the technological advantage and can afford to take the risk. On the other hand, because the approach is unique, many people wonder whether or not it is actually viable, and this skepticism is an obstacle to revenues.

A Difficult Problem

Since the introduction of logic synthesis as an EDA product more than twenty years ago, all synthesis tools have been built the same way: turn the RTL into gates, and then optimize that netlist to meet the placement constraints. The RTL is read in and reduced to a control/dataflow data-structure, which then is turned into gates and then the gate-level optimizer operates on the netlist until the design meets the timing constraints. At this point the netlist is ready for place and route.

This approach has worked well as long as features size on the die were large enough. But beginning at the 190 nm node, the electrical characteristics of the circuit began to significantly impact the functionality of a design that was constructed based solely on logic rules.

The physical characteristics of the constructed circuit are now so important that the number of design rules to be taken into account has increased dramatically. Physical synthesis products take rules that guide the physical representation of the circuit into account during the gate-level optimization phase and provide a netlist to the place and route tool that is more likely to function than if only logic rules had been applied. This approach presents two major problems: one is that execution time has increased considerably as circuit size increases, and the other is that almost always the verification of the placed circuit still reports rules violations.

The result is that designers have to manually complete a feedback loop between the synthesis tool and place and route tool. The size of the gates is so small now compared to the size of the connecting wires, that the electrical characteristics of the wires connecting the various logic blocks, and their placement relative to each other, are likely to change the functioning of the circuit.

The logical solution is to combine physical synthesis with place and route functions in one tool. Doing so provides both technical and financial advantages over the traditional method.

The Technical Side

It is abundantly clear that avoiding problems is more efficient than solving them. Although the design community in general has not yet shown to have fully incorporated this reality in its methods, Design Compiler 2010 appears to offer a strong tool to help designers follow the dictum. The new Synopsys tool and the Oasys Design Systems product, that has been available for a few months, allow engineers to combine logic synthesis with place and route starting at the RTL. Following a "Think Globally, Act Locally" approach, they provide designers with the ability of not only anticipate possible place and route problems that would result from a literal logic synthesis of RTL code, but to provide directions to avoid them before running the synthesis tool. The methods and algorithms used by the two companies are quite different, but the approach is similar. Approaching the problem at a higher abstraction level lowers execution times and improves quality of results.

Methods such as this one are a step forward because they eliminate the assumptions inherent in the more generic rules used by physical synthesis tools. Physical synthesis must follow the design rules established by the foundry with little if any knowledge of the intent of the specific design. Of course, while physical synthesis tools are a good step forward, they generate what at times are very difficult problems due to design rules violations resulting from the literal application of the rules. Some of these errors can be avoided by guiding the synthesis process and thus providing more intelligence to the place and route tool. The results is less rules violations, and a time savings (read cost savings) for designers.

Design Compiler 2010 and Real Time Designer send an important message to designers: what you do up front determines how difficult and costly your development flow will be. Although it may not be humanly possible to predict all the problems that are inherent in a particular design, all agree that designers can visualize the functional structure of a circuit even before running a synthesis tool. Design re-use, whether done with proprietary or third party blocks, aids significantly in determining the final topology of the circuit.

To be sure Synopsys has not integrated Design Compiler and IC Compiler into one product, but has significantly tighten the integration of both data and information between the two tools. It is clear that the value of Design Compiler 2010 is much greater when used with IC Compiler instead of a third party tool performing similar tasks.

Both Design Compiler 2010 and Real Time Designer are a step forward in increasing the level of abstraction and thus simplify the problem to be solved. There is of course a drawback. Designers used to a simpler set of rules for logic synthesis will now have to learn more about place and route, if they are to provide correct guidelines to a new tool.

The Financial Side

By incorporating place and route guidelines in Design Compiler 2010, Synopsys has significantly improved the advantage designer will enjoy when using the entire Synopsys flow, and not just Design Compiler as a point tool. The result, I expect, will be that more companies will decide to use the entire tool flow from Synopsys, instead of purchasing only licenses for Design Compiler. Thus the impact to the revenue flow should be greater than that of just new licenses for Design Compiler. In the same vein, Oasys avoids being "just another" alternative to synthesis, and provides an integrated path from RTL to circuit verification.

Of course both Synopsys and Oasys make another, more profound, impact to our industry: the diminishing importance of point tools. The vast majority of startups have as their most valuable asset a new point tool that improves a specific step in the design flow. The road to their success is to introduce their product in the existing design flow of some important design companies. In turn this will both gain visibility and impact the purchasing process to the extent that will cause one of the three leading EDA companies to purchase the startup. By providing a closer integration using its own tools, Synopsys is in a leadership role in demonstrating that flow integration that improves error avoidance is more important than localized improvements. A tool that has to solve both less and simpler issues can even afford to be a bit less run time efficient than a tool that has to solve difficult and more numerous problems. Startups, then, will either need to show much greater cost savings than before in order to become viable, or will have to solve more difficult problems, like Oasys has done..

More About Design Compiler 2010

To meet aggressive schedules for increasingly complex designs, engineers need an RTL synthesis solution that enables them to minimize iterations to speed up physical implementation. To address these challenges, topographical technology in Design Compiler 2010 is being extended to produce "physical guidance" to Synopsys' place-and-route solution, IC Compiler, tightening timing and area correlation to 5 percent while speeding up IC Compiler's placement phase by 1.5 times (1.5X).

A new capability allows RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Additionally, Design Compiler's new scalable infrastructure tuned for multicore processors yields 2X faster synthesis runtimes on four cores.

"Cutting design time and improving design performance are essential to keep our competitiveness in the marketplace," said Hitoshi Sugihara, department manager, DFM & Digital EDA Technology Development at Renesas Technology Corp. "With the new physical guidance extension to topographical technology we are seeing 5 percent correlation between Design Compiler and IC Compiler, up to 2X faster placement in IC Compiler and better design timing. We are adopting the new technology innovations in Design Compiler to minimize iterations while meeting our design goals in shorter timeframes."

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Reviews:
Review Article
  • Garbage in , Garbage out? April 13, 2010
    Reviewed by 'Ron Craig'
    Hi Gabe,
    In the days since I started working at 1.5um things have certainly progressed! Despite all these advances in increasing physical awareness during synthesis one important aspect hasn’t changed though – a poorly constrained design makes it almost impossible to efficiently close timing. At Atrenta we’ve seen numerous rudimentary problems encountered by our customers (clocks not reaching vast swathes of registers for example) which would unfortunately not have been addressed by physical awareness. We continue to see demand for our SpyGlass-Constraints validation and management solutions from leading edge users who simply can’t deal with the iterations they face in closing their constraints. And when you talk about timing exceptions things can start to get even more scary.
    If you really want to take a more abstract view of the problem, I’d suggest that we as an industry need to deal with the ‘garbage in, garbage out’ problem. The 2X runtime improvement you quote is certainly of value to users, but a bigger problem is the 15-20 iterations they need to go through before they have a set of timing constraints which they trust and which actually constrain their design completely. RTL Signoff is more than having good quality RTL, it’s about having all the ancillary data (timing constraints included) to actually make effective use of that RTL. Given the choice of chipping away at the problem in the backend or creating a much better starting point, I know which I’d go for.
    Cheers,
    Ron Craig
    Atrenta Inc.


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