Static timing analysis (STA) has been around more than 30 years. However, in the last fifteen years its importance has grown to the point that it has become an essential step in the design of digital circuits.
Initially STA was used to find hold and setup violations in the clock tree, due to logic errors by designers. Then as silicon geometries became smaller and smaller, circuit topology also needed to be taken into consideration. Logic circuits that seemed safe in theory, would at times experience glithches in signal transmission due to marginal clock distribution issues. The use of STA tools then became a required step in the certification of circuitry before producing a final tapeout.
As fabricated geometries shrank below the 90nm process node, the use of multiple clocks became a general approach to partition the design into both functional blocks and power distribution and use segments of the design. Cross talk and other sources of noise, which at best had always been second order effects, must now be taken into consideration in verifying and certifying an IC before release to manufacturing. STA is not only required, but the tools themselves must be more powerful and more complex, as they take more physical effects under consideration, deal with multiple clock trees, and handle much larger designs.
Over the last five years or so a few sign-off advancements such as composite current models (CCS) models, distributed multi-mode/multi-corner (MM/MC), and location-based on-chip variation (OCV) analysis have been incorporated into sign-off flows. Bigger design teams, bigger machines and more complicated analysis have also been leveraged to handle the increasing design complexity enabled by advanced process nodes.
While the STA timing analysis flow (load design, load constraints, load parasitics, update timing graph, produce timing reports) essentially remains the same, the combination of design complexity and the amount of analysis required for advanced technology nodes has raised the stakes for STA. As instance counts continue to double, the number of clocks is growing. Wading through multiple timing reports and evaluating the timing closure status and/or strategy can be exhausting.
Statistical STA (SSTA) was introduced with the intention of adding statistical variation analysis to the traditional STA-based sign-off flows. Using statistically-created libraries, designers can evaluate their design's susceptibility to variation. At 65 nm, traditional sign-off continued to produce working silicon using PVT-based sign-off and margins (OCV). At 40 nm and below, design teams are taking another long look at SSTA as a potential solution for improving yields and reducing timing analysis.
Sign-off tool capacity requirements are a major and costly problem for teams and the problem is exacerbated by the fact that the number of timing scenarios is doubling or tripling with each generation. At 28 nm, it becomes nearly intractable because 50 scenarios will be required for mainstream designs. To address this problem the only alternative has been to use more sign-off tool licenses and more hardware. Designers can run MM/MC timing analysis provided they have a sufficient number of STA licenses and number of machines. This drives costs and budgets up and runs exactly counter to the concept of a solution that qualifies as better.
With growing demand for consumer and hand-held products, IC designers need to reduce dynamic and static power to maximize battery life. Adoption of advanced technology nodes enables higher performance cells, more density per square millimeter and lower power. For the high-volume ICs targeted at hand-held devices, power requirements are more important than performance and many advanced power management techniques are used to minimize power.
As low power requirements drive supply voltages down below the 1V threshold, design teams have observed that standard delay models will not sufficiently address process variation. At 28 nm, transistors operating under 1V exhibit strong delay nonlinearity with respect to PVT parameter variations.
One viable solution for low-voltage 28-nm designs is to complement traditional corner-based STA with a statistical timing engine that supports nonlinear delay distributions. SSTA can be used to obtain an accurate estimate of design performance while limiting the number of timing iterations.
Designers, to be sure that a circuit will have acceptable yields and will executed as expected in the product, need advanced STA tools. Unfortunately the tools often require long execution times, even with expensive high end computing platforms. This is a major problem for companies trying to keep development costs as low as possible. They must contend not only with the non recurring cost of the computing machinery, but also, more importantly, with the time required between executions. With every design change, designers need to wait for the tool to finish executing, then they must analyze the results, make changes, perform another place and route function, go through circuit parameters extraction and then run STA again.
The Latest Entry
A few days ago Magma Design Automation announced its new timing analysis product: Tekton. For those who like to know where the name of the product came from, I can offer two origins. The word "tekton" is a Greek word that means "one who constructs", and thus Magma is saying that this product will help designers construct their IC. But, sticking with the geological nature, typically volcanic, of Magma's products, tekton is the Greek root of the English word tectonics, and can be found as a proper name to describe plate tectonics, the origins of earthquakes. Thus the product name would fall into the Magma family tree.
The company says that unlike other solutions, Tekton runs multi-scenario analysis efficiently on low-cost hardware without requiring a large number of expensive servers and software licenses. Leveraging breakthrough technology, this new platform addresses complex sign-off challenges and is suited for today's most challenging designs.
"The complexity of timing sign-off has reached crisis proportions, forcing design teams to re-evaluate resource planning, design architectures and final sign-off solutions," said Premal Buch, general manager of Magma's Design Implementation Business Unit.
Tekton has been designed to perform both parameter extraction and circuit analysis using parallel execution architecture, whether on single or multiple CPU machines. Taking advantage of the experience accumulated in STA applications over the years, Magma has been able to design a tool that addresses today's problems with today's architectures and algorithms. The company claims that the new product was designed to more efficiently handle on-chip-variation (OCV), composite current source (CCS) models and crosstalk analysis. The Tekton platform includes Tekton QCP. Its architecture enables multi-corner extraction with small increases in runtime as additional process, voltage and temperature (PVT) corners are added for each process node migration. Tekton and Tekton QCP can be used together in a single STA timing session.
To address the timing closure challenges design teams face at 40 nm and below, Tekton supports advanced OCV (A-OCV) margin reduction techniques. By incorporating A-OCV into timing closure flows, design teams can minimize global pessimistic margins that lengthen tapeout schedules and potentially increase die sizes. For critical path and net analysis, Tekton and Tekton QCP offer high accuracy modes that leverage Tekton's integrated SPICE engine and Tekton QCP's accurate extraction.
Magma has stated that Tekton and Tekton QCP used together produce results that are as accurate as Synopsys' Prime Time but use less computing resources while, at the same time, decreasing the Engineering Change Order (ECO) cycle by a factor of ten.
The Gold Standard
Magma's, as well as all other vendors', reference to Prime Time is a recognition that the Synopsys tool has been considered the Gold Standard STA tool in the industry almost since its introduction. The company has kept up with the increasing demands of more and more complex designs by expanding the original tool into a suite of products that now includes PrimeTime, PrimeTime SI, PrimeTime PX and PrimeTime VX. The tools in the suite take advantage of Synopsys HSPICE accuracy in circuit analysis.
In order to address the explosion in the number of scenarios which need to be verified, Synopsys introduced Distributed Multi-Scenario Analysis (DMSA) capability in Prime Time. DMSA allows designers to set up, distribute, run, and perform ECO fixes simultaneously across multiple scenarios, thereby reducing overall turnaround time.
Time-to-market pressure, chip complexity, and control of SI effects are all factors requiring an accurate, fast, and trusted analysis and signoff solution. With shrinking process geometries and rising clock frequencies for nanometer designs, signal integrity (SI) effects such as crosstalk delay and noise (or glitch) propagation can cause functional failures or failed timing. It is essential for designers to address these SI problems to ensure that their designs are delivered to market correctly in the shortest amount of time. PrimeTime SI extends Prime Time capabilities by adding accurate crosstalk delay, noise (glitch), and voltage (IR) drop delay analysis to address signal integrity effects at 90-nm and below.