nSys Announces Functional Coverage Test Suites for Major Standards/ Protocols

Newark — March 10, 2010 — nSys Design Systems, offering the world’s largest portfolio of Verification IPs, announced the availability of Functional Coverage Test Suites for its nSys Verification Suite (nVS) portfolio. The biggest challenge for Verification managers is to know when to stop verifying. With the advent of SystemVerilog, Coverage Driven Methodology is increasingly being used for measuring verification completeness. Coverage Driven Methodology checks whether all possible significant combinations of variables, assertions & transitions have been covered in verification.

“Our large customer base and deep knowledge of protocols has helped us define the most comprehensive set of coverage bins for each protocol/ standard,” says Atul Bhatia, CEO, nSys. “Achieving 100% Functional Coverage is a time consuming, iterative process. nSys’ test suites are ready-to-use, and help achieve 100% Functional Coverage in a single iteration.”

“We currently offer Functional Coverage Test Suites for all our major products, and the same will be available for our complete portfolio by the end of this quarter,” shared Atul.

About Functional Coverage Test Suites:
Functional Coverage is one of the most important components of constrained random verification strategy. 100% functional coverage means one has verified all possible aspects of the design. nSys facilitates designers in achieving complete, faster coverage by helping to check the entire functionality of their standards-based ASIC/ SoC designs.

About nSys: nSys offers the World’s Largest portfolio of Verification IPs for standard interfaces/ protocols such as PCIe Gen3/ Gen2/ Gen1, PCI-X, PCI, SR-IOV, Ethernet (100/ 40/ 10/ 1G), Interlaken, USB 3.0/2.0, SATA 3.0, SAS 3.0, ATAPI, AXI, APB, AHB, DDR3/2… Each nVS consists of BFM, Monitors, Assertion-based Checkers and Test Suites for Compliance Testing & Functional Coverage. All nVS are available in native SystemVerilog (OVM/ VMM) & Verilog, with option of Source Code. The nVS family of VIPs is integrated to work with popular languages, like ‘e’, SystemC, OpenVera and VHDL on all commonly used simulators and platforms. nSys also offers Verification Services like Independent Verification Services, SystemVerilog Migration and Verification Consulting. For more information, please visit www.nsysinc.com


Prachi Khaneja
nSys Design Systems Pvt. Ltd.
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