CSEM introduces a new generation of ultra low power DSP RISC cores for portable applications

Neuchâtel, — March 09, 2010 — The icyflex family of ultra low power 16/32-bit RISC processor cores developed by CSEM, the Swiss Center for Electronics and Microtechnology, offers a flexible architecture that allows for different combinations of control and DSP functionality. Three silicon-proven cores are so far available, consuming as little as 6 µW/MHz.

Portable products, whether for medical, consumer, industrial or home automation, have an increasing need for miniaturized low voltage and low power consumption electronics. While small low power micro-controllers are available, they often lack the data processing power required by modern system-on-chip solutions.

CSEM has been a pioneer in the field of low power, low voltage processors, from the original watch processors to the CoolRISC core and the MACGIC DSP. The icyflex architecture was developed as a flexible processor with both DSP and control-type capabilities and C-compiler support, with a best-in-class power budget. A high level of flexibility allows the architecture to be optimized for the application, ranging from simple control-type through to highly parallel audio/video signal processing applications. The result is a family of high performance processors with best-in-class energy efficiency.

Three variants are so far available:

  • icyflex1 - a 16/32-bit RISC processor for a mix of control and DSP-type applications, such as wireless sensor networks requiring local signal processing

  • icyflex2 - a smaller 16/32 bit RISC processor for control type applications with power consump-tion as low as 6 µW/MHz (in 65 nm LP CMOS)

  • icyflex4 - with a scalable architecture capable of some control and massive parallelism for com-putation-intensive DSP-type applications such as audio or video processing.

All three processors are available as VHDL soft blocks with multiple parameters (bus widths, stack size, optional blocks) so that only the part of the processor useful for the application is integrated. The processors can be configured at run time to add new addressing modes and new instructions to reduce the number of cycles for individual algorithms. The processors feature powerful data paths (up to 36 multiply-and-accumulate units) and high bandwidth busses to registers and memory for maximum throughput per instruction, or clock cycle. The processors are designed for testability and On-Chip-Debug support through a JTAG interface.

Development tools are available, based on the GNU tool suite (compiler, assembler, debugger, cycle accurate instruction set simulator, etc) with plug-in for the Eclipse IDE.

All icyflex processor cores are available either as IP cores under license, or as part of a low-power SoC design at CSEM.

CSEM will be demonstrating the icyflex at the Embedded World exhibition in Nuremburg 2-4 March (Hall 12, Booth 12-462, www.embedded-world.de)




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