A couple of other things. All of this software for designing chips is fairly complex. There are lots of knobs and parameters. So one of the other things we did, was that we created what we called flow manager. The basis of the flow manager is “I have a new customer. They have never used the system. They have a new design. They are under the gun. We need to give them 2 or 3 commands which became the flow manager so they can read that design in and get the GDSII very quickly.” The flow manager is basically templates. It has boiled down the entire flow to 2 or 3 commands. So if you are a new user, you can just load it up, put your design in, load the template and run it. It will automatically walk through all the steps. You can stop it. You can edit it. You can create your own template. We started with one template for what we call the basic practices for RTL to GDSII. We have added others. We have MPDD. We have the multimode decoder one. We are working on some to kind of help with the integration of some of the partner flows we have with the IP guys like ARM and MIPS. That’s one other piece for ease of use.
We talked about the common data model. Here’s another big difference, if I am a design house, lets say for the guy who wants to build a chip, an ASIC. You did all the RTL, you are the expert on what the chip has to do. I’m going to pay you to layout the chip. At some point, we are going to be sharing information. The beauty of Magma, if we are both using Magma. I’m working on layout. I get the timing. It is looking good except for this block. I don’t understand what you are trying to do there. You need to look at this. I write a command called Export Volcano. That creates what you can think of as a big file. In that file is everything, all the library data, all the design data, netlist. Everything I have done with the design, the constraints. You pick it up. I FTP it. You load it into your Magma system and now you are looking at exactly what I saw. You do not have to worry about reading in 150 different files and making sure you have the right versions. It is all self-contained. So you go in and you find and see exactly what is going on in this block. Why did this thing get placed in the corner? It should be over here. You spend an hour or so. You move it over here. You relook at it. You ship it back to me. I just read it in. It is a little bit of an aside. I wanted to explain what the Volcano is. Not everyone knows. What the hell a volcano is other than something that explodes? The Visual Volcano is basically a viewer that we have written into the system. This captures long textual reports, columns full of numbers. Basically it takes it and puts it in graphical form. It might be a pie chart, it might be a line chart or a table. It allows the guy who is debugging the system to very quickly (there are a lot of reports they can run) pinpoint where the hotspots or problems are and they can click on it and see exactly where in the design it is coming from. We call that the Visual Volcano.
Low power. I am seeing it as a theme for DAC this year. Everyone is talking about it. It is really clear, it is not just cell phones and iPods anymore but all of our customers are concerned about it. Today, four out of the top five wireless guys are using Magma. They employ a lot of different techniques.
Here is an example. These are all the different types of power reducing techniques that have been applied. These are all supported by the tool. Some are very common like clock gating. Others like DVSS are not so common. We scale voltage and frequency.
One of the techniques that is being used a lot is multiple voltage domains. Clearly, if you scale the voltage down, you can make big savings in power. We support what is called a virtually flat implementation. With the Magma system the number of power domains you have is equal to the number of different voltages that you are going to be running.
In this case you can see a lot of blocks running at .9V. The rest of it runs at 1V. The way it is handheld by our system, the way you as a designer interact with it , it is just two power domains (PD). Most systems, at least our competitors, if you have all these different blocks even if they were at the same lower voltage that is eight domains. What that means when you are doing the implementation, the final hooking and all the analysis, you are dealing with eight separate things. In our system you are dealing only with two separate things. We lump all of the .9 volt guys together. That pays big dividends. What that means is that you get the chip design done a lot faster because you are dealing with fewer entities.
One other key point. We are supporting two formats; UPF and CPF. We are the only vendor, at least that we are aware of, that is providing a full flow that supports the two formats. We have taken the position with our customers that we are not going to recommend one over another. You want to do UPF, have at it. We support that. You want to do CPF, have at it. We support it. Most of the other bigger vendors have chosen one or the other. We are playing Switzerland.
We talked about scenarios and design sizes. It is very clear that designs will get much bigger. It is also clear where flat designs can’t cut it. You will not be able to push 100 million gates flat through one system. The answer to that is a product we call Hydra that wraps around our Place & Route system. It basically automates taking a huge design, multi-hundred million gate design, breaking it into chunks, figuring out where the chunks go. Obviously, you as a designer tell it what the timing needs to be across the chip. It figures out how to budget the timing and all that. Then, it talks to the Place & Route tool. It is not just making wild guesses. That’s the best way I can explain it. There is a lot of stuff you can do. The idea is that it is kind of a designer’s tool to hierarchically attack the problem, break it up into smaller manageable chunks, implement them but know when you get to the end, you are actually going to have a chip that works. We just bailed out a customer who could not get the timing right. They would do a floorplan, and everything looked good. Then they would start implementing, get almost all the way done and realize that they would never meet timing. It’s very hard. This Hydra is really part of an effort we have to be able to solve 100 million gate chips and above that we know are coming, that we have already seen.
The main point I want to make is that the biggest change I have seen is that we have really fleshed out the pieces of the system that you need to be able to do a whole chip that certainly when I left Magma before, we had some powerful stuff but we did not have the whole picture.
There are so many different angles to this. Certainly low power is really important going forward. We are seeing that everywhere. It is not just how fast can you get your chip done and can you get timing closure but what techniques can I use to get the power down? That’s the big concern. The transition for some customers going to 40nm is a big don’t care. Some do not care because they are still at 130nm. But we have a lot that are moving, some from 65nm to 40nm. We have others making the jump from 90nm to 40nm. They are doing what we call a node jump. They are not even going to do 65nm. We have been very successful there.