What: EE Times Virtual Conferences are interactive events that incorporate online learning, live chat, active movement in and out of exhibit booths and sessions, vendor presentations and contests. The final panel discussion of the day at the System-on-Chip, Designing Next Generation SOCs virtual conference will cover "Economics of Next Generation SOC Design: A Node Too Far?" This panel will examine the state of the economics of different forms of SOC design, delve into specific areas of increasing costs (verification, etc.) and try to ascertain whether there is any relief on the horizon.
Who: Grant Martin, Chief Scientist, Tensilica
When: Wednesday, September 16, 5:00 - 6:00 p.m. ET
Where: This is a virtual conference so participants can join from any computer. For more information, visit http://www.eetimes.com/soc/
Tensilica, Inc. -- the leader in customizable dataplane processors -- is a semiconductor IP licensor recognized by the Gartner Group as the fastest growing semiconductor IP supplier in 2008. Dataplane Processor Units (DPUs) combine the best capabilities of CPUs and DSPs while delivering 10-to-100-times the performance because they can be customized using Tensilica's automated design tools to meet specific dataplane performance targets. Tensilica's DPUs power SOC designs at system OEMs and five out of the top 10 semiconductor companies for products including mobile phones, consumer electronics devices (including digital TV, Blu-ray Disc players, broadband set top boxes and portable media players), computers, and storage, networking and communications equipment. For more information on Tensilica's patented, benchmark-proven DPUs visit www.tensilica.com.
Contact: Erika Powelson Powelson Communications for Tensilica 831-424-1811 Email Contact