Tilera Adopts Broad Range of Cadence Solutions for Multicore Processor Design

SAN JOSE, CA -- (MARKET WIRE) -- Aug 25, 2009 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that fabless semiconductor company Tilera Corporation has utilized the full range of Cadence design technologies to develop its innovative, highly scalable multicore embedded processors.

As an innovative startup with a need for both fast time to market and highly complex design capabilities, Tilera® immediately embraced the benefits of selecting a full suite of design automation tools from Cadence, including Cadence® Encounter® technology for digital implementation, synthesis, test and equivalence checking; Incisive® technology for verification; Virtuoso® technology for schematic editing, and Allegro® technology for HDL design entry, among others.

"Cadence has been a vital collaborator in the design of our high-performance, low-power TILEPro™ family of processors," said John F. Brown III, Vice President of IC Engineering at Tilera. "The combination of their broad line of design, verification, and implementation software, design IP, and services delivered exactly what we needed to create the highest performance embedded processors. Cadence is our preferred design solution partner and our relationship continues to evolve and grow as we work on our next-generation projects."

Tilera's products developed using this environment include TILE64, TILEPro64, and TILEPro36 families of full-featured multicore processors spanning a range of processing and power requirements. With up to 64 complete cores on one chip, the design of these processors is among the most complex on the market today.

"At the outset, Tilera enlisted Cadence Services to help tune a design methodology that would reduce the overall project risk and assist them in implementing their multicore processor with incredible performance, power efficiency and programming flexibility characteristics," said Vishal Kapoor, Marketing Director for Services at Cadence. "Through our collaboration, which included Design and Verification IP in addition to model development for packaging, Tilera was able to quickly come up to speed on the design methodology and, in short order, has developed and is shipping production units of three families of multicore processors designs. It's a powerful testament to the flexibility and breadth of Cadence solutions."

About Tilera

Tilera Corporation is the industry leader in highly scalable general purpose multicore processors for networking, wireless, and multimedia infrastructure applications. Tilera's processors are based on its breakthrough iMesh™ architecture that scales to hundreds of RISC-based cores on a single chip. The distributed nature, of Tilera's revolutionary architecture, and the standards-based tools, including ANSI C/C++ compiler, GNU tools and Eclipse IDE, deliver an unprecedented combination of performance, power efficiency, and programming flexibility. Tilera was founded in October 2004, and now offers two product families: TILE64™ processors and TILEPro™ processors. The company is headquartered in San Jose, Calif., with locations in Westborough, Mass., Shanghai, and Beijing. More information about the company and its products is available at www.tilera.com.

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, the Cadence logo, and Encounter are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

For more information, please contact:
Dan Holden
Cadence Design Systems, Inc.
408-944-7457

Email Contact





Review Article Be the first to review this article

Synopsys: Custom Compiler

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Real Intent: Leveraging on Investments
More Editorial  
Jobs
Analog Hardware Engineer for Teradyne Inc at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
Field Application Engineer for Teradyne Inc at San Jose, CA
Upcoming Events
CODES+ISSS 2017, Oct 15-20, 2017, Lotte Hotel, Seoul, South Korea at Lotte Hotel Seoul Korea (North) - Oct 15 - 20, 2017
DVCon 2017 Europe, Oct 16 - 17, 2017, Munich, Germany at Holiday Inn Munich City Centre Munich Germany - Oct 16 - 17, 2017
11th International Symposium on Networks-on-Chip (NOCS 2017) at Seoul Korea (South) - Oct 19 - 20, 2017
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise