It is not unusually for people during their professional careers to move from one company to another but it is relatively unusual for one to return to a company that they have left. What brought you back to Real Intent after a couple years elsewhere with other small companies?
That's a good question. The two years I spent at Real Intent previously went very well. I was instrumental in bringing in some new formal technologies to Real Intent's products that had very good impact on the market competitiveness of our products. The reason I left had nothing to do with Real Intent. It was more an opportunity to found a company in a different space that I thought would be challenging. That said, in a sense I never left because over the last few years I have maintained close communication with Prakash, in terms of the direction that Real Intent was taking and possible opportunities. When I saw the opportunity to come back I took it because, as I said earlier, that verification is one of the most important challenges that our industry faces today. It continues to be the show stopper in terms of realization of the next four to five technology shrink generations. It is really mind-boggling to consider the complexity of designs with one-half to one billion gates on a single chip and of getting them out in a reliable and predictable way. I am basically a technologist. I sort of feed off of on such fundamental challenges. I am coming back to Real Intent because I see myself as being able to contribute to addressing these challenges.
The complexities in the design of these chips are coming from a number of different directions. It is sort of a multiheaded beast. These challenges are a combination of the timing complexity of these chips, the system complexity as a result of many diverse components, and from the raw complexity of the number of transistors on these chips. And also, going forward, the power and reliability management structures on chips are becoming more complex. Handling all of these things in a predictable manner is a very interesting challenge.
Real Intent, over the years, has established itself as a leader in the chip verification space. Chip verification is interesting in the sense that the longevity of a company is a significant plus. The longer you are in this space and the more tapeouts you have participated in, the more competent you become and the greater recognition you get in the design community.
Real Intent at this point has 30 to 40 customers. It has been around for about a decade. Possibly hundreds of tapeouts have depended on Real Intent. I feel good joining a company with this strong foundation. It provides me an excellent platform to innovate and be in the thick of things as far as being able to participate in addressing chip design challenges.
Editor: While at DAC I sat next to a Chief Technologist quite by accident. He was not only a CT but also a full professor at a well respected university. He was not a CTO as the university does not allow its professor to be an officer in a company. The company was founded by some of his former students and has subsequently hired many more of his former students. He said he had nothing to do with the business side. When he told his wife that company had offered him the position, she said he could take it, only if it had nothing to do with the business side because he was such a lousy business man. He spends more time with the company than with the university and has taken a few leaves of absence. He travels the world talking about technology. At the table were two Europeans, one from STMicro and one from Infineon. He spoke of meetings with their associates the previous week in two different European countries. He spoke of leveraging the network of contacts he has built up over the years in the research community both in academia and industry as a way of keep track of what is going on. He agrees with Pranav about the need for the CTO to have a deep understanding of the company's technology, the possible application of that technology and related technologies to help drive the technical direction of the company.
How big a company is Real Intent?
About 30 people worldwide.
What is the revenue stream?
We are a privately held company and do not give out that information.
Would you provide us an overview of Real Intent?
Real Intent is a design verification company that offers an innovative cocktail of formal methods, structural analyses and simulation-based methods to verify key aspects of a design like functionality and timing. The company fundamentally believes in the power of formal methods. It also believes that naive application of formal methods is not net productive. We believe in what we call "automatic formal". This is a philosophy that permeates all our products, where the checking to be done is almost completely extracted automatically from the design description itself and the application of formal methods is judicious and under the hood. The role of the designer in terms of telling the tools what needs to be checked is very minimal. This is consistent with the name of the company, Real Intent! Real Intent is focused on the verification of the intent that the designer probably implied without the designer having to explicitly spell it out. The goal of all of our products is to minimize the designer's overhead. Underlying the tools are formal methods, structural analysis and simulation hooks to check the extracted checks automatically and comprehensively.
Currently the company has three product families. There is a product family called Ascent associated with checking the functional aspects aspects of a design. It extracts basic functional checks automatically from the RTL and then applies simulation and formal methods to perform the checking.
The second family of products is called Meridian. Its role is to check the design around clock domain crossings. Clock domain crossings have become an extremely important part of a design today partly because the raw diversity of components on chips has grown by leaps and bounds. You have a number of different kinds of components (USB, Ethernet, …) and also the design itself. Everything on a single die. All these different components feed off different clocks and of course communicate with each other. You have a whole lot of these clocks asynchronous relatively that communicate with each other. Multiple domains are also necessitated by the difficulty in distributing a single clock to the entire chip in a predictable manner.
Checking a design in the context of this type of asynchronous communication is extremely difficult. It is extremely hard to find these errors in simulation or even in the lab. The manifestation of these errors may actually only take place on a specific sample of chips from the foundry. In that sense Meridian provides an extremely important service to the design community by being able to catch these errors early on.
The third family of products is called PureTime. The role of PureTime is to check timing constraints that are commonly specified in the context of a complex design today and also parallelize these timing constraints in a formal manner. Timing errors can be insidious in that timing errors are very hard to find through simulation. PureTime will likely become an important part of the design flow because of its capability to find timing problems early.
So three product families.