San Francisco, Calif., July 27, 2009 — Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, today announced at the 46th Design Automation Conference (DAC) major extensions to its 1Team®-Genesis platform. 1Team-Genesis supports architectural level chip assembly and provides a rich set of capabilities to plan the design, automate its assembly and establish feasibility. Along with the industry standard SpyGlass® platform for RTL analysis and optimization, Atrenta provides a fully integrated flow from early specification to RTL handoff for implementation.
The announcement includes enhancements to the existing 1Team-Genesis Assembly product and the introduction of two new products: 1Team-Genesis IO and 1Team-Genesis Registers.
Enhancements to 1Team-Genesis Assembly include support for IP-XACT version 1.4, complete RTL import from either Verilog or VHDL and extensive support for hierarchical design management and editing. The newly introduced 1Team-Genesis IO supports functions such as I/O pin multiplexing, local/global selection and the ability to visualize ball grid and bonding diagrams.
1Team-Genesis Registers provides support for the hardware/software interface, including register management and the ability to generate register RTL. A graphical user interface also supports the capture of hierarchical memory maps.
“Our advanced digital television chips require automated assembly and sophisticated I/O support,” said Dr. Kang, Yong-Seok, principal engineer of Design Technology Part at LG Electronics, Inc. “We are pleased with the results we have seen so far using Atrenta’s 1Team-Genesis. We plan to use the product for automated assembly and I/O configuration on our latest designs.”
"It is our goal to provide a structured SoC assembly methodology with the 1Team-Genesisis platform," said Sameer Patel, senior director of marketing at Atrenta. “These new additions to the 1Team-Genesis platform bring us much closer to realizing our vision. We also continue to work closely with IP providers to enable seamless integration of their IP into the 1Team-Genesis Assembly solution. I’m delighted that our customers are recognizing the productivity benefits of our automated SoC assembly solution and have started achieving good results during deployment.”
For more details regarding Atrenta’s collaboration with IP providers for 1Team-Genesis, see Atrenta’s July 7 press announcement on this topic.
Atrenta is providing a full demonstration of the integrated 1Team-Genesis platform in booth 1528 at DAC. Conference participants may learn more about the product by attending User Track: Front-End Power Planning and Analysis, session 9.3s, “New SoC Integration Strategies for Multi-Million Gate, Multi-Power/Voltage Domain Designs”, presented by Texas Instruments.
1Team-Genesis Assembly, 1Team-Genesis IO and 1Team-Genesis Registers are all available now. Pricing for the product depends on configuration and starts at $300K for a 1 year time-based license.
Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com. Atrenta, Right from the Start!
Atrenta, the Atrenta logo, SpyGlass, and Early Design Closure are registered trademarks of Atrenta Inc. All others are the property of their respective holders.
This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.
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