Satin IP Technologies Helps STMicroelectronics Achieve IP Design Quality Closure

Companies to jointly present at DAC 2009 on enabling IP quality closure


MONTPELLIER, France – July 13, 2009 – Satin IP Technologies, the company that delivers design quality closure with fast return on investment, has been working with the Home Entertainment and Display (HED) product group of  STMicroelectronics on how to monitor and improve the quality of their internally developed semiconductor intellectual property (IP) blocks.

 

With systems-on-chip (SoCs) now comprised of more than 50 IP blocks, the quality of IP deliveries is a key factor to ensure risk-free integration and predictable schedules. To help improve IP quality, STMicroelectronics has defined design standards over time, along with a design flow to implement them. However, with the growing complexity of both the IP blocks and the design flow, the quantity of data to be monitored had become too big to authorize continuous and accurate quality monitoring with ad hoc techniques. ST’s HED product group now uses Satin IP’s VIP Lane® to extract key data from their IP design flow and to achieve on-the-fly quality monitoring during the development cycle. VIP Lane also provides automated production of IP integration documents and easier supervision of all the IP blocks of a given SoC.

 

“VIP Lane adds new capabilities to the quality design flow that HED has been working on for years,” said François Rémond, CAD & design methodology director at ST’s HED product group. “These enlarged capabilities lead to faster identification of quality metrics requiring special attention, better communication between IP and SoC design teams and measured savings on design time-to-integration.”

 

 “ST has a long history of defining design practices and deploying tools for developing IP blocks that integrate smoothly. These practices and tools led to the definition of quality metrics that VIP Lane was able to automate to help ST with monitoring and deployment. And ST can maintain these metrics in the long term,” said Michel Tabusse, CEO of Satin IP Technologies.

 

In the User Track session at DAC 2009 on Wednesday, July 29th, from 1:30 – 3:00, Satin IP and ST’s HED product group will present information on how design quality closure applies to a family of IP blocks for the 55nm set-top-box SoC, and will outline the measured benefits.

 

 

About Satin IP Technologies

Committed to design quality closure with fast return on investment (ROI), Satin IP Technologies delivers software solutions for fact-based design quality monitoring. Working within customers' design flows, VIP Lane® turns customers' design practices for IP blocks or SoCs into a robust set of quality criteria and automates the implementation and documentation of design quality metrics at no extra cost in engineering time or resources. VIP Lane shortens time-to-market by delivering effective flow integration and on-the-fly quality monitoring at zero overhead to design teams. Satin IP is a privately-held company with headquarters in Montpellier, France. For more information, see www.satin-ip.com

 

VIP Lane® is a registered trademark of Satin IP Technologies. All other product or service names are the property of their respective owners. All rights reserved.

 

#          #          #

Media Contacts:

Europe: Michel Tabusse, Satin IP, @ +33 (0)467 13 00 87

North America: Linda Marchant, Cayenne Communication, (USA) 919-451-0776,

Email Contact




Review Article Be the first to review this article
Aldec Webinar Nov 30

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Computer History Museum: the Future of War is Here
More Editorial  
Jobs
REVISED***Director Product Line RF/IC for EDA Careers at San Jose, CA
Principal PIC Hardware Controls Engineer for Infinera Corp at Sunnyvale, CA
ASIC Design Engineer for Infinera Corp at Sunnyvale, CA
Senior SW Developer for EDA Careers at San Jose, CA
Senior PIC Test Development Engineer for Infinera Corp at Sunnyvale, CA
Upcoming Events
“Empowering Leadership with WIT and WISDOM” at SEMI 673 South Milpitas Blvd. Milpitas CA - Nov 28, 2017
Artificial Intelligence and Convolution Neural Networks Discussion at San Jose State University Student Union Theater San Jose CA - Dec 4, 2017
Silicon Valley's Only Comprehensive Embedded Systems Conference at San Jose Convention Center 150 W. San Carlos St. San Jose CA - Dec 5 - 7, 2017
Oski Technology’s Decoding Formal Club Meeting at The Conference Center San Jose CA - Dec 7, 2017



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise