Avery Design Systems Announces Support for PCI Express 3.0 Verification IP

ANDOVER, Mass. — (BUSINESS WIRE) — July 9, 2009 — Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced that its PCI-Xactor verification IP solution now supports the PCI Express® (PCIe®) 3.0 draft standard, at a preliminary revision 0.5, and is available to existing customers under active maintenance. PCI-Xactor from Avery Design allows customers to increase verification productivity and confidence in designs targeting the evolving PCIe 3.0 standard which delivers 8.0 GT/s performance and advanced features for the graphics, server, network and computer markets.

“PCI Express 3.0 warrants critical design updates to the PHY layer of the PLX family of switch devices, and getting this correct the first time is an absolute necessity given our critical time-to-market windows,” said Vijay Meduri, Vice President of Engineering, PLX Technology. “Avery is one of our important partners in ensuring interoperability with the ecosystem.”

"IP products for verification of PCI Express systems, such as those from Avery Design Systems, offer significant value to the PCI-SIG community," said Al Yanes, PCI-SIG Chairman and President. "Avery Design has been an active participant in the PCI Express design ecosystem for several years, and we appreciate their contributions which help to streamline the deployment of PCI Express technology into the industry."

"Avery is a trusted partner in the development of our PCI-Express PHY and Controller IP products. We use Avery's PCI-Xactor Verification IP, as do our customers, for validating operation and compliance," said Ewald Liess General Manager of Snowbush IP, a Division of Gennum Corporation. "The timely release of PCIe 3.0 support in PCI-Xactor is an important element that helps our validation and supports the emerging 3.0 ecosystem."

Avery’s PCI-Xactor is a complete functional verification solution for PCI Express 1.1/2.1/3.0 and SR-IOV including feature rich models that work in any verification languages including SystemVerilog OVM and VMM methodologies, comprehensive protocol checking, functional coverage monitoring, and dedicated core and chip-level compliance test suites for Root Complex, Endpoint, SR-IOV Endpoint, Switch, and PHY designs.

"We are committed to work with our chip and systems customers and IP partners to provide a total chip, controller, and PHY verification solution for the evolving PCIe 3.0 standard to lower their risk and time to market associated with bringing next generation products to market, while delivering robust and superior solutions," said Chris Browy, Vice President of Avery Design Systems.

Upcoming Events

See Avery Design Systems at the PCI-SIG Developers Conference 2009 (Booth #7) on July 15-16, and the Design Automation Conference (Booth #1724) on July 26-31.

About Avery Design Systems

Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of symbolic simulation and formal analysis for bug hunting and coverage closure, robust core-through-chip-level Verification IP for PCI Express, SATA, and USB standards, and scalable distributed parallel logic simulation. The company is a member of the Synopsys SystemVerilog and VMM Catalyst Programs, Mentor Graphics Modelsim Value Added Partnership (VAP) program, and has established numerous Avery Design VIP partner program affiliations with GDA Technologies, Snowbush, and CAST. More information about the company may be found at www.avery-design.com.



Contact:

Avery Design Systems
Chris Browy, 978-689-7286
Email Contact




Review Article Be the first to review this article
Aldec

Featured Video
Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
Fall Schedule: A Host of Must-attends
More Editorial  
Jobs
Senior Methodology Automation Engineer for EDA Careers at San Jose, CA
Senior R&D Engineer...Timing Closure Specialist for EDA Careers at San Jose or Anywhere, CA
Senior Front-End RTL Design AE for EDA Careers at San Jose, CA
DDR 3-4-5 Developer with VIP for EDA Careers at San Jose, CA
Proposal Support Coordinator for Keystone Aerial Surveys at Philadelphia, PA
Upcoming Events
11th International Conference on Verification and Evaluation of Computer and Communication Systems at 1455 DeMaisonneuve W. EV05.139 Montreal Quebec Canada - Aug 24 - 25, 2017
The Rise of Mechatronics at Dassault Systèmes San Diego 5005 Wateridge Vista Drive San Diego CA - Sep 12, 2017
The Rise of Mechatronics at Buca di Beppo - Pasadena 80 West Green Street Pasadena CA - Sep 13, 2017
S2C: FPGA Base prototyping- Download white paper



Internet Business Systems © 2017 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy