Rambus to Present New Innovations and Demonstrate High-Speed Memory Technologies at Denali MemCon

(BUSINESS WIRE) — June 23, 2009 Rambus Inc.:


  Rambus Inc.


Denali MemCon 2009
Hyatt Regency Santa Clara
5101 Great America Parkway
Santa Clara, CA
Booth #15


June 22-24, 2009

Join Rambus at MemCon 2009 for papers, demonstrations, and displays of its high-performance memory technology innovations including:

Rambus Demos and Displays

  • Silicon demonstration of a complete XDR™ memory system running at data rates up to 7.2Gbps with superior power efficiency. The XIO memory controller demonstrates bi-modal operation with support for both XDR DRAM as well as next-generation XDR2 DRAM.
  • The Mobile Memory Initiative featuring a silicon test vehicle achieving 4.3Gbps data rate at best-in-class power efficiency.

Rambus Presentations

Wednesday, June 24 - 9:45 a.m. – 10:15 a.m.

  • Michael Ching, director of Strategic Development, will discuss the future of main memory subsystems beyond DDR3 SDRAM, which must attain faster data rates than 1600MHz while maintaining low power, access efficiency and competitive cost. This discussion will also outline some of the key challenges facing future main memory, and the Rambus innovations that can be applied to advance the main memory roadmap.

Wednesday, June 24 - 4:00 p.m. – 4:30 p.m.

  • Fred Ware, Technical Director, will discuss the increasing application demands of mobile consumer platforms and the performance importance of the underlying memory subsystems. This discussion will outline innovations developed by Rambus as part of its Mobile Memory Initiative and how these technologies address the issues of scalability, power efficiency, power state exit latency, clock recovery, signal integrity, and low-cost packaging.

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