Atrenta SpyGlass®-MBIST Adopted by STMicroelectronics for RTL Memory BIST and Repair Insertion

SAN JOSE, Calif. — (BUSINESS WIRE) — June 11, 2009 Atrenta Inc., the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow, today announced that STMicroelectronics has released Atrenta’s SpyGlass®-MBIST (memory built-in self test) insertion solution as part of its front-end design kit. This kit is accessible to all ST design teams worldwide as well as ST’s ASIC customers.

The SpyGlass-MBIST solution is the result of a strategic collaboration initiative between Atrenta and STMicroelectronics for automating the insertion of ST’s proprietary memory test and repair in advanced technology nodes at 65nm, 45nm and 32nm.

The SpyGlass-MBIST solution is the industry’s first RTL memory BIST insertion tool to be independent of BIST IP technology, and works with any supplier’s qualified ASIC design kit and BIST libraries. The solution allows replacement of the original memories in a design with the BIST system at RTL as well as insertion of the repair solution, if required. The technology also facilitates replacement or insertion of BIST inserted blocks at the SoC level, along with top level connection of the signals.

“The integration of Atrenta’s SpyGlass-MBIST solution in our front-end design kit has automated ST’s proprietary embedded memory test and repair capabilities at RTL. The solution not only allows early and faster validation at RTL, but also allows timing optimization of the complete RTL with memory BIST where area impact is known early,” said Frederic Grandvaux, Memory Test Solutions manager within Central CAD & Design Solutions, STMicroelectronics.

The SpyGlass-MBIST flow is flexible and allows the user to define design-specific information or change the tool’s default values. The MBIST insertion can be run at both the gate and the RTL levels. The other benefit of BIST insertion at the RTL level is that SpyGlass-DFT rules can be run at RTL including the MBIST logic for achieving high (>99%) testability early in the design stage.

“We have three designs in advanced phase of development that rely on inserting memory test with the SpyGlass-MBIST solution. This automatic solution becomes necessary in devices having huge proliferation of memory instances, as our applications require improving efficiency/lead time in our DFT design flow,” said Angelo Oldani, design director for the Communication Infrastructure Division, STMicroelectronics.

“We are delighted to be working with STMicroelectronics to extend our capabilities in the area of memory test and repair,” said Kiran Vittal, product marketing director for test and power products at Atrenta. “The SpyGlass-MBIST technology is a significant enhancement to our existing family of test products – SpyGlass-DFT for RTL stuck-at test analysis, and SpyGlass-DFT DSM for RTL at-speed test analysis. With this technology, we are proud to offer the broadest solution in the industry to support Early Design Closure for inserting and validating design-for-test at RTL.”

The SpyGlass-MBIST product is available now, and the U.S. list price starts at $90,000 for a one-year time based license.

About Atrenta

Atrenta is the leading provider of Early Design Closure® solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com. Atrenta, Right from the Start!

Atrenta, the Atrenta logo, SpyGlass, and Early Design Closure are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.



Contact:

Atrenta Inc.
Charu Puri, +1-408-467-4254
Corporate Marketing
Email Contact
or
Lee PR
Ed Lee, +1-650-363-0142
Email Contact




Review Article Be the first to review this article
Cadsoft: CS EAGLE Version7.3 Learn MORE


Editorial
Peggy AycinenaWhat Would Joe Do?
by Peggy Aycinena
#52DAC: Rumors & Realities
Peggy AycinenaIP Showcase
by Peggy Aycinena
Sonics: Busy Days, Dark Silicon Knights
More Editorial  
Jobs
Sr. Field Applications Engineer, CA for Real Intent at Sunnyvale, or San Diego, CA
Engineering Technology Director for Atrenta at San Jose, CA
P&R SW Developer AUSTIN for EDA Careers at San Jose, CA
6 SR. Account Manager openings California and TX for EDA Careers at San Jose, CA
Application Engineer Valley for EDA Careers at San Jose, CA
Application Engineers Valley/Austin for EDA Careers at San Jose, CA
Upcoming Events
SEMICON West 2015 at MOSCONE CENTER SAN FRANCISCO - Jul 14 - 16, 2015
Semicon West 2015 July 14 - 16, 2015 San Francisco, CA at Moscone Center 1700 4th St San Francisco CA - Jul 14 - 16, 2015
SpyGLASS by Atrenta
S2C: FPGA Base prototyping- Download white paper
DownStream: Solutions for Post Processing PCB Designs



Internet Business Systems © 2015 Internet Business Systems, Inc.
595 Millich Dr., Suite 210, Campbell, CA 95008
+1 (408) 850-9202 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy