Would you give us an overview of Tanner EDA’s product suite?
Consider the flow chart below.
One of the things I would mention is flexible licensing. We have noticed that some of our competitors go out of their way to restrict licensing. You can only use a license within a certain country for example. So, if you have a staff that rotates around the world in different time zones, you can not reuse the same license. We do not have those kinds of restrictions. We go out of our way to make licensing flexible. We have this thing called a converter license. A customer can check out a license for a few days and put it on their laptops. If they have to go on a plane, they can do chip design. If they go fishing, they can do chip design in their cabin in the woods. Wherever they need to be, they can take their license with them.
Our products are almost entirely perpetual license based. If a customer wants to do time-based license, we are more than happy to accommodate a subscription base but for the most part we have stuck with perpetual licensing. Our thought there is that the customer really prefers a perpetual license. Our big competitors switched a number of years ago to time-based license as a way to temporarily reduce the cost to the customer (their prices are so high) and then to hook the customer so that their software will quit running, if they do not continue to pay the vendor. We do not believe in that kind of hook with the customer. We want them to continue to pay us maintenance, if they feel they are getting value from the improvements made to the tool. The result of this though is that we do have to have a continual stream of innovations and new capabilities, not only introducing new tools but continuing to add capabilities to old tools. The improvements are based upon customer feedback to make their lives easier or more productive.
What about the individual products?
Tanner Tools are fully-integrated solutions consisting of front end tools for schematic capture, circuit simulation, and waveform probing, and back end tools for physical layout and hierarchical, foundry-compatible design rule checking (DRC) verification.
Front end tools include S-Edit for schematic capture, T-Spice for simulation, W-Edit for waveform analysis and HiPer Simulation for Verilog-A
One of our new things with T-Spice simulation is support for Verilog-A behavioral language, so you can have both circuits and behavior together. W-Edit is our waveform viewer and analysis tool.
For physical layout tools we have several different DRC tools. One of them is interactive DRC (L-Edit Interactive DRC). It does not do the most advanced DRC but it runs while you are drawing. That allows people to get it right the first time, instead of finding the error very downstream and having to correct it then.
Schematic driven layout is a big important part of our tool suite. People can do their schematic in S-Edit and bring that netlist or a netlist from some other editor into L-Edit. It does a manual assist. You can do the placement and it shows you the fly lines. As you route the fly lines, it updates. We have just introduced SDL router to do the routing for you automatically. We have standard place and route which is the sole entry on the digital side of things for small gate counts digital parts and digital subsystems you need to add to the analog. You can use our standard cell P&R. There is a device generator tool that produces complex multi-fingered transistors of different aspect ratios according to the parameters that you set up.
For physical verification tools there is Verification tools hierarchical extract and DRC, standard DRC (L-Edit DRC), standard LVS (L-Edit LVS) and HiPer Verify for foundry compatible DRC and netlist extraction. HiPer Verify is Calibre compatible, the only low cost Calibre compatible extractor and design rule checker. It puts us in a very unusual position where in one case we have allied with them but compete with them elsewhere. So we have a love-hate relationship.
Node highlighting with L-Edit NHL is one of the new capabilities where you can poke on some piece of your layout and see where that electrical node extends. HiPer PX (Parasitic Extractor) is a new tool that allows you to extract parasitic resistance and capacitance at a much higher accuracy level.
We also offer a set of specialty tools important to some customers but not to others such as TFT routing, dummy fill and pad report.
Recently introduced capabilities include cross probing of layout or schematic from the netlist. We can provide this, because we engineer our tools from the ground up to work together. We can do some activities between tools that are more difficult to do with other vendor suites that were not engineered together. HiPer Verify now supports Dracula Extaract decks and Assura rule decks. A 64-bit engine enables all of our tools to run on Windows-64 which allows customers to break to 2 GByte memory limit. There are not a whole lot of customers that have designs that big but it is growing in importance.
We provide Linux support with identical features to our Windows version. L-Edit now has T-Cells, programmable cell equivalent. People want to write code to algorithmically construct some of their layout.
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