by Sameer Patel, Sr. Director Marketing, Atrenta
Semiconductor suppliers will need to start looking at alternative design techniques such as platform-based design and IP reuse to drive down the cost of design starts and more importantly, amortize these costs over several applications (or generations thereof) in order to get the desired ROI.
The killer app of this decade has clearly been the " Smartphone" - handheld devices such as the iPhone or the BlackBerry that can enable consumers to read e-mail, text friends, create spreadsheets and documents, watch YouTube, play video games, listen to music, take pictures, store them, get directions, and yes, also make phone calls.
This convergence of applications has resulted in increasing demands on the chips that power these devices. Semiconductor suppliers are being asked to deliver more and more performance while at the same time consuming less power to extend battery life.
With the global economic meltdown, the design challenge has been exacerbated for semiconductor design teams as they are now being asked to deliver more with fewer resources than before. The only way this can happen is by boosting the productivity of design teams significantly.
Another major reality in the semiconductor marketplace is that the cost of a new design start at 45nm or below is now approaching (or will even exceed) $50M. Given this, a market size of roughly $500M for the targeted application is needed in order to justify the investment in the design start. The key question is how many such killer apps exist out there (besides the iPhone) that can boast such a market size?
Therefore, to implement these techniques, it will become imperative to build SoC assembly methodologies that facilitate reuse, manage complexity, time-to-market and development costs. A company which can adapt quickly and cost-effectively to differing requirements from multiple customers is likely to gain market share, especially in the current recessionary environment.
Figure 1: Key components of a structured SoC assembly methodology
In order to build a structured SoC assembly methodology, semiconductor suppliers need to integrate various components (as shown in Figure 1) in a seamless manner. At the heart of such a methodology is the basic connectivity solution that allows designers to easily browse and import IP's from a variety of sources, including 3rd party, legacy and internally developed. The next step is to integrate the bus fabric into the SoC and then follow that up by integrating the other subsystems, such as power management, I/O's, clocks, resets, interrupts, test, etc. Today, most of these sub-systems are hand-crafted and managed through custom scripts written by the SoC architects or their CAD design resources. This requires several man-months of design effort per sub-system. The solutions are very design-specific and not scalable across multiple designs and much less across multiple applications.
I believe that there is a tremendous opportunity in the industry to boost design team productivity by automating the generation of these different "fabric" sub-systems through a library of generators. The basic architecture of a particular fabric could be defined by the appropriate architect through a series of general tables and templates and then the design-specific information can be provided at the time of execution (instantiation) to generate design-specific sub-systems.
Some of this infrastructure exists today and is leveraged during the generation of standard bus fabrics. However, if a broader, standard infrastructure was fully defined and made available to designers world-wide through a toolkit (perhaps supported by a commercial vendor), one can envision a burgeoning ecosystem of sub-system generators that would be written by the smartest architects around the world for use on designs targeted for specific applications.
This is analogous to Apple Inc. providing an application toolkit to developers around the world to develop apps for its iPhone platform. We have seen how quickly this resulted in some very useful (and cool!) applications being available for consumers with varying interests. The cost of developing these apps is minimal and the end-user can download such apps for minimal cost. Now, imagine having a solid user community like that for SoC design, wherein a SoC architect could quickly download the specific sub-system generators for his design and through some minor customization (which could be enabled by commercial software) integrate them into their SoC design methodology in a matter of days.
This would go a long way toward driving down the overall cost of doing SoC design and shorten design cycle times. Most importantly, this could give the semiconductor industry the much-needed stimulus to target the next wave of killer apps that will drive us out of this global recession.
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Editorial contact: Amy Battrell, Email Contact, 650-363-0142