The Future of EDA and the Semiconductor Industry, One Man’s View

To what extent do you need to use the same tools as your customers? How do the design flows dovetail?
In a GDSII handoff, we do not care what they use. A GDSII file is a GDSII file and everyone converges there. If it is a netlist handoff, the bulk of our work is done with Magma tools. There is no reason that a chip that was designed with front tools from Synopsys or Cadence can not be laid out with tools from Magma. So that’s not a problem. If we do the spec handoff, which is rare, we define the tool flow, so there is no issue by definition. The flows that we work through do not have a bearing on our interface to the customer. The handoffs are at logical points where you can make tool changes. Obviously, if our customer did half of the layout with Cadence tools and asked us to finish it with Magma tools that would be a non-starter. There are fortunately logical places in the methodology that we use, standard methodology in the industry, which allows these things to happen very gracefully.

Do you have any proprietary tools that give you an advantage or is it a matter of standard tools used by people with greater expertise?
We do not make EDA tools at all. Where we do spend a fair bit of time and money is in writing scripts and infrastructure that automates the tools further. We do not want to be in the business of writing tool shells around EDA products or writing that interface to EDA products. What we do is write sophisticated shells that let the methodology run without human intervention and as fast as possible. From an EDA perspective, we look much like a large IDM would in terms of facilitating the EDA purchases they have made and staying away from polluting or contaminating those tools with home grown code, which I can tell you with some level of expertise, is a mistake. Having said that, we have an in-house software development team. What they write is infrastructure tools. In the last nine years we have built and patented on many different occasions an internal methodology or infrastructure we call eSilicon Enterprise. Basically, what we have done is to write a semiconductor business-to-business, a business application B2B – there was a time we would have been embarrassed to say that – that sits on top of an Oracle ERP and production control system. What that allows us to do is to manage dozens of chips electronically with very little human intervention and virtually no error. We have spent a fortune developing tools that purge errata out of the database from our supply chain which we access automatically, purge out the mistakes and post them to an Oracle database which we didn’t see any reason to reinvent. Then we publish that with our own tools back to the Internet so our employees and our customers watch the production occur in virtually real time and capture any delays or shortcomings immediately. So our customers don’t wait for our sales guys to come back from vacation to find out where their chips are. They can log on and see that they are at metal level 4 and moving to metal level 5 in 12 hours. The same is true for delivery schedules. What’s been ordered, what’s been backordered? That is done electronically and allows us to have many, many fewer people and offer a much higher quality of service to customers and allow us to achieve every transaction for every chip. If you think about it, our worst performing chip is still someone else’s baby. So we might not be so excited about keeping track of the details of a poorly performing chip but we do it anyway because it is critical to our customers. Anyone who has tried to run a business like us with spreadsheets and Microsoft is not getting it. It is just impossible.

How do you charge for your service?
We have two places where invoicing takes place. One is the non-recurring engineering where people say “Please do the physical design. Can you get the test program written, the mask. etc? Can you get this ready for production? For a 65nm chip that runs from $2 million to $3 million. And we make the bulk of our money shipping silicon. We make a chip that has cost x and we bill it to you for y. The delta is our gross profit. The interesting thing is that while our customers are always looking to have lower cost - they are always under pressure too – we can point to their collective rationality: “Why engage with us, if we are not cheaper than you can do it yourself? We have not fooled 100 customers. They are smart people. The same spreadsheets we have. We make a chip for them of super high quality at a price point less than or equal to what they could do. The rate at which we sign up new customers is testimony to that factor.

In dollars per wafer or per chip, is it cost plus?
It is not cost plus. Over the years there have been a few cost plus situations where it was unique and warranted. But generally speaking, we quote a price to a customer. We guarantee that price. We typically guarantee them two, three or four price breaks in terms of time and volume. And we take the yield risk. Our customer can know that they can acquire that part hell or high water for the price we quoted them as opposed to a promise from the opps team. And if the opps team guys are wrong, what do they do? It costs more. It is that simple. By the way, they are never right. They turf a lot of the cost over to R&D and Marketing and to everywhere but the COGS or the chip. What happens is that the CEO or CFO says “Those things didn’t cost us $9, they cost $12 when I add it all up.” Where do you go? In our case, if we quote $19 and heaven forbid it costs $11, then we eat that. So our customers know absolutely, positively that they are not paying us more for that part than what we quoted them in the timeframe we quoted it. There’s a great value in there. There is a great risk mitigation factor that executives understand. The operations people do not.

In January 2008 eSilicon acquired SwitchCore’s product lines. How does that fit in to eSilicon strategy?
SwitchCore was a unique case, an atypical acquisition. It was a company that had missed a generation or two of new products and yet they had a couple of products in the market shipping successfully. Due to the direction of their Board, they elected to get rid of their semiconductor business. So they sold us the product lines and we continue to service their customer installed base. We do not seek new design wins. We don’t do anything to support the product, only supply chain continuity. It is order fulfillment. We acquired those product lines. We do have any op expense or R&D around them. The customers, by the way, are delighted. We are an ongoing entity that is happy to supply them, whereas they were buying the chips from a company that was winding down and going out of business. The customer is happy. We are happy. We are selling chips with no op expense except the margin. The company was happy. They got a soft landing for something that wanted to shut down. Candidly, we are getting a lot of these calls now. There is a lot of small to medium sized companies that are sort of the walking wounded. They don’t have good prospects. Their cash balances are waiting yet they have products they have been shipping for two, three or four years to customers in industries that will have demand for 10 to 12 years. We are in conversations with a lot of folks who are looking to arrange a transaction whereby we take them out of that situation and compensate them today. They get a soft landing and their customers are happy.

You have said a lot about the way people will be doing semiconductor production in the future. Smaller companies will look to outsource because they can’t support the fixed cost of maintaining operations. How does this impact the future of EDA vendors?
I think that EDA is in a world of hurt. The business has been flat for 10 years. It is the only member of the semiconductor supply chain that gets paid regardless of success. Everyone else shares in the success of the production or in the failure of the production. Even IP, that takes an upfront fee, gets compensated in large measure on royalties based on volume shipments. There is that one mini exception. But everyone else lives and dies on the same side of the table as the firm making the chip except for EDA. The market place has simply rejected that. The irony from my perspective is that few industries add more value to the world than EDA. With no EDA, there is no semiconductor industry. With no semiconductor industry, there is no IP infrastructure. This is a trillion dollar industry driven off a $4 billion market segment because their business model is broken. Until they start to accept the risk of production in one form or another, they will always be relegated to a tax and therefore not appreciated or valued. You take that background, you add your point that the number of design starts is shrinking every single year and they are being aggregated into companies like mine. Who do they sell to and for what? If you are going to do one 65nm chip or one 45nm chip a year, how many tools do you need? If those products are being rapidly deployed and outsourced to fabless ASIC companies like mine, I have all the tools I need. I am not going to buy more. What does EDA do other than fight over the existing shrinking market which is what they are doing today? They are a world of hurt.

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Review Article
  • Great interview. Very insightful.... March 05, 2009
    Reviewed by 'EDA Observer'
    Thank you Mr Horgan for this insightful interview. I remember when Cadence acquired CCT.
    Paying $1 billion for a comapany with just $15 million in revenues shows how Cadence-Synopsys rivalry and their legal battles in the context of an "irrationally exuberant" stock (and M&A) market fueled decisions by Cadence exectives that explain partially why Cadence is where it is today.

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  • Full circle or Half circle?? March 04, 2009
    Reviewed by 'Anil Nadig'
    We started the semiconductor industry with one company coming up with the architecture, write the RTL, do the layout with thier in-house tools and fabricate in their own fab (AKA IDMs). Then we shed the fabrication saying its too costly to maintain and invest in RnD (The Foundary company?), and then the in-house tools sayings its cumbersome to develop (EDA vendors?) and spawned off the layout-ing to a third party saying too much overhead because of fixed costs (Esilicon?). But the future seems to be "specalized" "Value chain producers" with access to foundry to be able to have insight into nanometer issues (DFM?) and in-house developed tools with the knowledge gained from foundry to have edge over competitors. Which means the future seems to be putting back atleast half (in-house foundry and in-house tools) of the things, that we shed for various reasons into, one company. Half circle?? May be a day will come when you may want to integrate these "specialized" "value chain producers" back to the architucture and RTL team for some reason thats not yet foreseen. That would be the full circle!!!. At least the near to middle term seems to be the half circle for sure.

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  • The Future of EDA March 03, 2009
    Reviewed by 'Jeff Liu'
    The Future of EDA and the Semiconductor Industry, One Man’s View

      One person of 3 found this review helpful.

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