Teklatech’s FloorDirector™ Tool Compatible with Sigrity’s XcitePI Power Integrity Simulation Flow

Santa Clara, CA, Feb-24 2009 -- Teklatech, a technology leader in SoC floorplanning and clock distribution solutions, and Sigrity, a technology leader in power and signal integrity analysis, announced today that Teklatech’s FloorDirector™ software has been proven compatible with Sigrity’s chip-level power integrity simulation flow. Based on a multi-processor SoC design, Sigrity has verified the compatibility of FloorDirector with Sigrity’s state-of-the-art XcitePI technology. It has been shown that with FloorDirector’s current signature analysis engine and XcitePI’s power grid extraction and simulation engine working together, SoC design engineers can easily perform what-if analysis on various system-level design changes, to identify potential design issues through the simulation of spatial variation of dynamic voltage noise distribution across the chip. This effort promotes open interoperability between Sigrity and Teklatech to deliver IR drop and noise aware SoC floorplanning and power integrity sign-off with considerably improved turn-around-time.

"We are impressed by Teklatech’s vision and extremely pleased to work with them. IC designers using Sigrity’s XcitePI now have access to a seamless interface to Teklatech’s FloorDirector to aid them with handling dynamic IR drop issues, especially within complex nanometer designs" said Jiayuan Fang, CEO and founder of Sigrity.

"Our FloorDirector tool provides dynamic IR drop and noise aware SoC floorplanning, and validating FloorDirector benefits with Sigrity’s simulation flow is a significant step forward for our mutual customers." said Tobias Bjerregaard, CEO at Teklatech. The FloorDirector clock- and floorplanning tool is used to achieve control over dynamic power peaks in System-on-Chip (SoC) designs. Its DPS technology (dynamic power shaping) reduces dynamic IR drop and supply noise by flattening power peaks, thus improving signal and power integrity, and helps designers achieve EMC compliance.

Sigrity’s physical power integrity tool, XcitePI, performs both frequency and time domain simulations to enable the best possible understanding of dynamic noise that can impact chip power integrity. Analysis of the full-chip power grid can be done incorporating fully distributed package effects to determine the existence and severity of power integrity issues including those that only show up when a chip is designed into a system. XcitePI facilitates effective design improvement with a range of visualization options to show the impact of changes in capacitor locations along with changes to bump, pad and the power grid designs. This helps design teams avoid costly late stage design respins.

About Sigrity
Sigrity, Inc., a privately held U.S. company incorporated in 1998, delivers advanced software solutions for package physical design and for analyzing power and signal integrity in chips, packages and printed circuit boards. Sigrity’s patented electrical analysis methodologies run orders of magnitude faster than general-purpose electromagnetic tools, helping leading companies in the semiconductor, computer, graphics, communications and networking industries ensure high performance and reduce time to market. The company is headquartered in Santa Clara, Calif., with global distribution to more than 185 customers through direct sales and representatives worldwide. For more information about how to ensure operational designs by using Sigrity’s package physical design and power and signal integrity analysis solutions, please visit: www.sigrity.com

About Teklatech
A technology visionary and industry pioneer, Teklatech provides targeted electronic design automation (EDA) solutions to the semiconductor market. With innovations in floorplanning and clock distribution networks Teklatech is focused on meeting the stringent demands of next-generation semiconductor industry.

By utilizing Teklatech's technology, IC designers can overcome the critical dynamic voltage drops and digital noise that may cause silicon failure. Teklatech's patented technology enables companies to eliminate costly silicon re-spins and achieve faster time-to-market of smaller, faster, more profitable semiconductor products that exploit the full potential of nanometer technologies. Privately held, Teklatech has received funding from world-class venture capital firms and industry leaders. Please visit: www.teklatech.com

For more information contact:
Leslie Landers, Sigrity, Inc.
Tel: (408) 260-9344 ext. 148;
Email: Email Contact

Sharon Akler, Teklatech
Tel: +45-25236851;
Email: Email Contact

Review Article Be the first to review this article

Featured Video
More Editorial  
ASIC/FPGA Design Engineer for Palo Alto Networks at Santa Clara, CA
Staff Software Engineer - (170059) for brocade at San Jose, CA
Technical Support Engineer EU/Germany/UK for EDA Careers at N/A, United Kingdom
Lead Java Platform Engineer IOT-WEB for EDA Careers at San Francisco Area, CA
Mechanical Designer/Engineer for Palo Alto Networks at Santa Clara, CA
Technical Support Engineer for EDA Careers at Freemont, CA
Upcoming Events
Zuken Innovation World 2017 at Hilton Head Marriott Resort & Spa Hilton Head Island NC - Apr 24 - 26, 2017
2017 SEMICON Southeast Asia at SPICE Arena Penang Malaysia - Apr 25 - 27, 2017
EDI CON China 2017! at Shanghai Convention & Exhibition Center of International Sourcing (SHCEC) No.2739 West Guangfu Road Putuo District, Shanghai (200062) China - Apr 25 - 27, 2017
2017 IoT Developers Conference at Santa Clara Convention Center California - Apr 26 - 27, 2017

Internet Business Systems © 2017 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy